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參數(shù)資料
| 型號： | ADN2817ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADN2817/ADN2818
Data Sheet
Rev. E | Page 16 of 40
Table 10. Control Register, CTRLA
fREF Range
Data Rate/DIV_FREF Ratio
Measure Data Rate
Lock to REFCLK
D7
D6
Range
D5
D4
D3
D2
Ratio
D1
D0
Set to 0
10 MHz to 25 MHz
0
1
Set to 1 to measure data rate
0 = lock to input data
Set to 0
Set to 1
25 MHz to 50 MHz
0
1
2
1 = lock to reference clock
Set to 1
Set to 0
50 MHz to 100 MHz
0
1
0
4
Set to 1
100 MHz to 200 MHz
n
2n
1
0
256
Table 11. Control Register, CTRLB
Config LOL
Reset MISC[4]
Initiate Freq Acquisition
Reset MISC[2]
D7
D6
D5
D4
D3
D2
D1
D0
0 = LOL pin normal
operation
1 = LOL pin is static LOL
Write a 1 followed
by 0 to reset MISC[4]
Write a 1 followed
by 0 to initiate a
frequency acquisition
Set
to 0
Write a 1 followed
by 0 to reset MISC[2]
Set
to 0
Set
to 0
Set
to 0
Table 12. Control Register, CTRLC
Configure LOS
Squelch Mode
D7
D6
D5
D4
D3
D2
D1
D0
Set to 0
0 = active high LOS
0 = squelch CLK and DATA
Set to 0
1 = active low LOS
1 = squelch CLK or DATA
Table 13. Control Register, CTRLD
CDR Bypass
Disable
DATAOUT Buffer
Disable
CLKOUT Buffer
Initiate PRBS
Sequence
PRBS Mode
D7
D6
D5
D4
D3
D2
D1
D0
Function
0 = CDR enabled
0 = data buffer enabled
0 = CLK buffer enabled
Set to 0
Write a 1 followed
by 0 to initiate a
PRBS generate
sequence
0
Power-down PRBS
1 = CDR disabled
1 = data buffer disabled
1 = CLK buffer disabled
0
1
Generate mode
1
0
Detect mode
Table 14. Control Registers, CTRLE/BERCTLB
Enable BERMON
BER Stdby Mode
PRBS/DDR Enable and Output Mode
D7
D6
D5
D4
D3
D2
D1
D0
Function
Set
to 0
Set
to 0
1 = BERMON
enabled
0 = BERMON
disabled
1 = place BERMON
in low power
standby mode
0 = BERMON
ready
Set to 0
0
Normal data rate output mode
0
1
Offset decision circuit (ODC) output mode1
0
1
0
Enable DDR mode (double data rate mode)
0
1
Offset decision circuit (ODC) output in DDR mode1
1
0
1
Enable PRBS detector/generator
All other combinations reserved
1
See AN-941 Application Note, BER Monitor User Guide.
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