參數(shù)資料
型號： ADMC401-ADVEVALKIT
廠商： Analog Devices, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-5 RoHS Compliant: No
中文描述： 單芯片，基于DSP的高性能電機控制器
文件頁數(shù)： 22/60頁
文件大?。?/td> 417K
代理商： ADMC401-ADVEVALKIT
REV. B
ADMC401
–22–
Entering Power-Down
The power-down sequence is initiated by applying a high-to-low
transition on the
PWD
pin or by setting the power-down force
control bit (PDFORCE) of the SPORT1 autobuffer/power-
down control register. The DSP core then vectors to the non-
maskable power-down interrupt vector at address 0x002C. Care
must be taken to ensure that multiple power-down interrupts do
not occur or else stack overflow may result. The interrupt ser-
vice routine at address 0x002C can be used to execute any num-
ber of housekeeping instructions prior to the processor entering
the power-down mode. Typically, this is used to configure the
power-down state, disable on-chip peripherals and clear pending
interrupts. The DSP subsequently enters the power-down mode
when it executes the IDLE instruction (while
PWD
is asserted).
The processor may take either one or two cycles to power down,
depending on internal clock states during execution of the IDLE
instruction. All register and memory contents are maintained in
power-down. Also, all active outputs are held in whatever state
they are in before going into power-down. If an RTI instruction
is executed before the IDLE instruction, the processor returns
from the power-down interrupt and the power-down sequence is
aborted.
Exiting Power-Down
The power-down mode can be exited with the use of the
PWD
pin or with the
RESET
pin. There are also several user-select-
able modes for startup from power-down which specify a start-
up delay as well as specify the program flow after startup. This
allows the program to resume from where it left off before
power-down, or for the program context to be cleared. Applying
a low-to-high transition on the
PWD
pin will take the processor
out of power-down. The amount of time it takes for the proces-
sor to come out of power-down is controllable with the
delay
startup from power-down
control bit (XTALDELAY, Bit 14 of
the Power-Down Control Register or SPORT1 Autobuffer
Control Register). If this bit is cleared, no additional delay over
the quick startup (100 cycles) is introduced. If this bit is set, a
delay of 4096 cycles is introduced.
The context for exiting power-down is set by Bit 12 (PUCR) of
the Power-Down Control Register. If this bit is cleared, after
exiting power-down the processor will continue to execute in-
structions following the IDLE instruction after the low-to-high
transition on the
PWD
pin. When the RTI instruction is en-
countered in the interrupt service routine for the power-down,
operation is returned to the main routine. If the PUCR bit is
set, for a “clear context”, the processor resumes operation from
power-down by clearing the PC, STATUS, LOOP and CNTR
registers. The IMASK and ASTAT registers are cleared and the
SSTAT goes to 0x55. The processor starts execution at address
0x0000.
Active output pins retain their states during power-down. In
addition, interrupts are latched and can be serviced if the
ADMC401 exits power-down with PUCR = 0. It is possible to
clock data into or out of the serial ports during power-down
by supplying an external serial clock. Data clocked into the
ADMC401 will remain in the RX registers. These activities
cause additional power consumption.
If
RESET
is activated while the ADMC401 is in the power-
down mode, power down is exited, and a normal Full System
Reset Sequence is initiated, (which depends upon the settings of
MMAP and BMODE for the boot method as usual). When
exiting power-down with
RESET
, the XTALDELAY control bit
is ignored.
Startup Time After Power-Down
The time required to exit the power-down state depends on the
method used to exit power-down. Unlike the standard ADSP-
21xx products, the XTALDIS bit of the Power-Down Register
has no effect on the ADMC401 so that it is not possible to avoid
the power drain caused by the XTAL pin toggling. When the
processor comes out of power-down by either the
PWD
or
RESET
pins, it will begin executing after a maximum startup time of
100 CLKIN cycles as long as the clock oscillator is stable and at
the same frequency as before power-down.
If the external clock is unstable when the ADMC401 exits
power-down, the XTALDELAY control bit can be used to
insert an additional 4096 cycle delay into the startup time. This
delay can only be inserted when the ADMC401 is brought out
of power-down by the
PWD
pin.
If the processor is taken out of power-down by the
RESET
line,
and the clock is stable and at the same frequency as before
power-down, the
RESET
need only be held for five cycles.
The PWDACK Pin
The PWDACK pin is an output that indicates when the ADMC401
is in the power-down mode. This pin is driven high by the pro-
cessor when it has powered down. It is driven low after the
processor has completed the power-up sequence. A low level on
the PWDACK pin also indicates that there is a valid CLKOUT
signal and that instruction execution has begun.
When power-down is terminated with the
RESET
pin or a start-
up delay is selected, a low level on the PWDACK pin only indi-
cates the start of oscillations on the CLKOUT pin. It will not
necessarily indicate the start of instruction execution.
The state of PWDACK and also the CLKOUT signal is unde-
fined during the first 100 cycles of the initial reset.
Using Power-Down as a Nonmaskable Interrupt
The power-down interrupt is never masked. It is possible to use
this interrupt for other purposes, if desired. The ADMC401 does
not go into power-down until the IDLE instruction is executed.
If an RTI is executed instead, before an IDLE instruction, the
processor returns from the power-down interrupt service outline
and the power-down sequence is aborted.
THE ANALOG-TO-DIGITAL CONVERSION
SYSTEM
OVERVIEW OF ADC SYSTEM
The ADMC401 contains a fast, high accuracy, multiple-input
analog-to-digital conversion system with simultaneous sampling
capabilities. This A/D conversion system permits the fast, accu-
rate conversion of currents, voltages and other signals needed in
high performance motor control systems. A functional block
diagram of the entire ADC system is shown in Figure 16.
The ADC system permits up to eight dedicated analog inputs all
to be converted in under 2
μ
s (at 26 MHz) through a single 12-
bit pipeline flash ADC. The entire ADC system (including
multiplexing and the sample and hold amplifiers) operates at a
clock rate equal to a quarter of the DSP instruction rate. Analog
input voltages of up to 4.0 V p-p can be converted. The input
signals are divided into two banks of four signals each, with
VIN0 to VIN3 making up one bank and VIN4 to VIN7 making
up the second bank. There are also two dedicated inputs (ASHAN
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