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參數(shù)資料
| 型號： | ADMC326YR |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller |
| 中文描述： | 28 - ROM的鉛基于DSP的電機控制器 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大小： | 219K |
| 代理商： | ADMC326YR |
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ADMC326
–8–
REV. A
DSP CORE ARCHITECTURE OVERVIEW
Figure 3 is an overall block diagram of the DSP core of the
ADMC326, which is based on the fixed-point ADSP-2171. The
flexible architecture and comprehensive instruction set of the
ADSP-2171 allow the processor to perform multiple operations
in parallel. In one processor cycle (50 ns with a 10 MHz CLKIN)
the DSP core can:
Generate the next program address.
Fetch the next instruction.
Perform one or two data moves.
Update one or two data address pointers.
Perform a computational operation.
This all takes place while the processor continues to:
Receive and transmit through the serial port.
Decrement the interval timer.
Generate three-phase PWM waveforms for a power inverter.
Generate two signals using the 8-bit auxiliary PWM timers.
Acquire four analog signals.
Decrement the watchdog timer.
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations as well as providing support for division primi-
tives. The MAC performs single-cycle multiply, multiply/add,
and multiply/subtract operations with 40 bits of accumulation.
The shifter performs logical and arithmetic shifts, normalization,
denormalization and derive-exponent operations. The shifter
can be used to efficiently implement numeric format control, in-
cluding floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC326 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value in
one of four modify (M registers). A length value may be associ-
ated with each pointer (L registers) to implement automatic
modulo addressing for circular buffers. The circular buffering
feature is also used by the serial ports for automatic data trans-
fers to and from on-chip memory. DAG1 generates only data
memory address and provides an optional bit-reversal capability.
DAG2 may generate either program or data memory addresses
but has no bit-reversal capability.
Efficient data transfer is achieved with the use of five internal
buses:
Program memory address (PMA) bus.
Program memory data (PMD) bus.
Data memory address (DMA) bus.
Data memory data (DMD) bus.
Result (R) bus.
Program memory can store both instructions and data, permit-
ting the ADMC326 to fetch two operands in a single cycle—
one from program memory and one from data memory. The
ADMC326 can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The ADMC326 writes data from its 16-bit registers to the 24-bit
program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit pro-
gram memory to a 16-bit data register, the lower eight bits are
placed in the PX register.
The ADMC326 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP interrupts comprise a serial
port receive interrupt, a serial port transmit interrupt, a timer
interrupt, and two software interrupts. Additionally, the motor
control peripherals include two PWM interrupts and a PIO
interrupt.
The serial port (SPORT1) provides a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed and unframed data transmit and receive
modes of operation. SPORT1 can generate an internal program-
mable serial clock or accept an external serial clock.
A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every
n
processor
cycles, where n–1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an interrupt
is generated, and the count register is reloaded from a 16-bit
period register (TPERIOD).
The ADMC326 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 50 ns pro-
cessor cycle (for a 10 MHz CLKIN). The ADMC326 assembly
language uses an algebraic syntax for ease of coding and read-
ability. A comprehensive set of development tools supports
program development. For further information on the DSP
core, refer to the
ADSP-2100 Family User’s Manual,
Third Edition,
with particular reference to the ADSP-2171.
Serial Port
The ADMC326 incorporates a complete synchronous serial
port (SPORT1) for serial communication and multiprocessor
communication. The following is a brief list of capabilities of the
ADMC326 SPORT1. Refer to the
ADSP-2100 Family User’s
Manual
, Third Edition, for further details.
SPORT1 is bidirectional and has a separate, double-buffered
transmit and receive section.
SPORT1 can use an external serial clock or generate its own
serial clock internally.
SPORT1 has independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame synchronization signals are active high or inverted,
with either of two pulsewidths and timings.
SPORT1 supports serial data word lengths from 3 bits to 16
bits and provides optional A-law and
μ
-law companding ac-
cording to ITU (formerly CCITT) recommendation G.711.
相關PDF資料 |
PDF描述 |
|---|---|
| ADMC326 | 28-Lead ROM-Based DSP Motor Controller |
| ADMC328 | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達控制器) |
| ADMC330 | Single Chip DSP（digital signal processing） Motor Controller(單片的數(shù)字信號處理馬達控制器) |
| ADMC330BST | Single Chip DSP Motor Controller |
| ADMC401BST | Single-Chip, DSP-Based High Performance Motor Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADMC326YR-XXX-YY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOTOR CONTROLLER |
| ADMC328 | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TN-XXX-YY | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
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