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參數(shù)資料
| 型號： | ADM8697 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Microprocessor Supervisory Circuits(微處理器監(jiān)控電路) |
| 中文描述： | 微處理器監(jiān)控電路（微處理器監(jiān)控電路） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 172K |
| 代理商： | ADM8697 |
ADM8696/ADM8697
REV. 0
–4–
PIN FUNCT ION DE SCRIPT ION
Pin No.
Mnemonic
ADM8696
ADM8697
Function
V
CC
V
BAT T
V
OUT
3
1
2
3
—
—
Power Supply Input +3 V to +5 V.
Backup Battery Input.
Output Voltage, V
CC
or V
BAT T
is internally switched to V
OUT
depending on which is at
the highest potential. When V
CC
is higher than V
BAT T
and L L
IN
is higher than the reset
threshold, V
CC
is switched to V
OUT
. When V
CC
is lower than V
BAT T
and LL
IN
is below the
reset threshold, V
BAT T
is switched to V
OUT
. V
OUT
can supply up to 100 mA to power CMOS
RAM. Connect V
OUT
to V
CC
if V
OUT
and V
BAT T
are not used.
0 V. Ground reference for all signals.
Logic Output.
RESET
goes low whenever LL
IN
falls below 1.3 V and remains low for 50 ms
after LL
IN
goes above 1.3 V.
RESET
also goes low for 50 ms if the watchdog timer is en-
abled but not serviced within its timeout period. T he
RESET
pulse width can be adjusted as
shown in T able I.
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period,
RESET
pulses low and
WDO
goes low. T he timer resets
with each transition at the WDI input. T he watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V,
PFO
goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
Power Fail Output.
PFO
is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. T he comparator is turned off and
PFO
goes low when V
CC
is below
V
BAT T
.
Logic Input. T he input to the CE gating circuit. Connect to GND or V
OUT
if not used.
Logic Output.
CE
OUT
is a gated version of the
CE
IN
signal.
CE
OUT
tracks
CE
IN
when LL
IN
is above 1.3 V. If LL
IN
is below 1.3 V,
CE
OUT
is forced high.
Logic Output. BAT T ON goes high when V
OUT
is internally switched to the V
BAT T
input.
It goes low when V
OUT
is internally switched to V
CC
. T he output typically sinks 7 mA and
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V
OUT
.
Logic Output.
LOW LINE
goes low when LL
IN
falls below 1.3 V. It returns high as soon as
LL
IN
rises above 1.3 V.
Logic Output. RESET is an active high output. It is the inverse of
RESET
.
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3
μ
A internal pull-up. See
T able I and Figure 4.
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog timeout period. T he timing can also be
adjusted by connecting an external capacitor to this pin. See T able I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.
Logic Output. T he Watchdog Output,
WDO
, goes low if WDI remains either high or low
for longer than the watchdog timeout period.
WDO
is set high by the next transition at
WDI. If WDI is unconnected or at midsupply,
WDO
remains high.
WDO
also goes high
when
LOW LINE
goes low.
No Connect. It should be left open.
Voltage Sensing Input. T he voltage on the low line input, LL
IN
, is compared with a 1.3 V
reference voltage. T his input is normally used to monitor the power supply voltage. T he
output of the comparator generates a
LOW LINE
output signal. It also generates a
RESET /
RESET
output. T he comparator output also controls the battery switchover circuitry.
T his is a special test pin using during device manufacture. It should be connected to GND.
GND
RESET
4
15
5
15
WDI
11
11
PFI
9
9
PFO
10
10
CE
IN
CE
OUT
—
—
13
12
BAT T ON
5
—
LOW LINE
6
6
RESET
OSC SEL
16
8
16
8
OSC IN
7
7
WDO
14
14
NC
LL
IN
12
13
2
4
T EST
—
1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADM8697AN | 功能描述:IC SUPERVSR MPU ADJ/RESET 16DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| ADM8697ANZ | 功能描述:IC SUPERVSR MPU ADJ/RESET 16DIP RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| ADM8697ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Microprocessor Supervisory Circuits |
| ADM8697ARU-REEL | 功能描述:Supervisor Push-Pull, Push-Pull 1 Channel 16-TSSOP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 類型:備用電池電路 受監(jiān)控電壓數(shù):1 輸出:推挽式，推挽式 復位:高有效/低有效 復位超時:最小為 35 ms 電壓 - 閾值:1.3V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:16-TSSOP 標準包裝:1 |
| ADM8697ARW | 功能描述:IC SUPERVSR MPU ADJ/RESET 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
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