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參數資料
| 型號： | ADM697AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, CDIP16 |
| 封裝： | CERDIP-16 |
| 文件頁數： | 2/12頁 |
| 文件大?。?/td> | 407K |
| 代理商： | ADM697AQ |
ADM696/ADM697–SPECIFICATIONS
P
arameter
Min
Typ
Max
Units
Test Conditions/Comments
V
CC
Operating Voltage Range
V
BATT
Operating Voltage Range
3.0
2.0
5.5
V
CC
– 0 3
V
V
BATTERY BACKUP SWITCHING (ADM696)
V
OUT
Output Voltage
V
CC
– 0.05
V
CC
– 0.5
V
BATT
– 0.05
V
CC
– 0.025
V
CC
– 0.25
V
BATT
– 0.02
1
0.6
V
V
V
mA
μ
A
I
OUT
= 1 mA
I
OUT
≤
100 mA
I
OUT
= 250
μ
A, V
CC
< V
BATT
– 0.2 V
I
OUT
= 100 mA
V
CC
= 0 V, V
BATT
= 2.8 V
5.5 V > V
CC
> V
BATT
+ 0.2 V
T
A
= +25
°
C
V
in Battery Backup Mode
Supply Current (Excludes I
OUT
)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
1.95
1
–0.1
–1
+0.02
+0.02
μ
A
μ
A
mV
mV
mV
V
mA
μ
A
Battery Switchover Threshold
V
CC
– V
BATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short Circuit Current
70
50
20
Power-Up
Power-Down
0.4
I
SINK
= 1.6 mA
BATT ON = V
OUT
= 2.4 V Sink Current
BATT ON = V
OUT
, V
CC
= 0 V, Source Current
7
1
0.5
25
RESET AND WATCHDOG TIMER
Low Line Threshold (LL
IN
)
Reset Timeout Delay
Watchdog Timeout Period, Internal Oscillator
1.25
35
1.0
70
4032
960
50
1.3
50
1.6
100
1.35
70
2.25
140
4097
1025
V
ms
s
ms
Cycles
Cycles
ns
mV
V
V
V
V
V
μ
A
V
CC
= +5 V, +3 V
OSC SEL = HIGH, V
CC
= 5 V, T
A
= +25
°
C
Long Period, V
CC
= 5 V, T
A
= +25
°
C
Short Period, V
CC
= 5 V, T
A
= +25
°
C
Long Period
Short Period
V
IL
= 0.4, V
IH
= 3.5 V, V
CC
= 5 V
I
SINK
= 10
μ
A, V
CC
= 1 V
I
SINK
= 400
μ
A, V
= 2 V, V
= 0 V
I
SINK
= 1.6 mA, 3 V < V
CC
< 5.5 V
I
SOURCE
= 1
μ
A, V
CC
= 5 V
I
SINK
= 1.6 mA,
I
SOURCE
= 1
μ
A, V
CC
= 5 V
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET
Output Voltage @ V
= +1 V
RESET,
RESET
Output Voltage
4
200
0.4
0.4
3.5
LOW LINE
,
WDO
Output Voltage
0.4
3.5
1
Output Short Circuit Source Current
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
3
25
V
CC
= 5 V
1
0.8
V
V
μ
A
μ
A
3.5
20
–15
50
WD1 = V
OUT
, (V
CC
) T
A
= +25
°
C
WD1 = 0 V, T
A
= +25
°
C
–50
POWER FAIL DETECTOR
PFI Input Threshold
PFI–LL
IN
Threshold Difference
PFI Input Current
LL
IN
Input Current
PFO
Output Voltage
1.2
–50
–25
–50
1.3
±
15
±
0.01
±
0.01
1.4
+50
+25
+50
0.4
V
mV
nA
nA
V
V
μ
A
V
CC
= +3 V, +5 V
V
CC
= +3 V, +5 V
I
SINK
= 1.6 mA
I
= 1
μ
A, V
= 5 V
PFI = Low,
PFO
= 0 V
3.5
1
PFO
Short Circuit Source Current
3
25
CHIP ENABLE GATING (ADM697)
CE
IN
Threshold
0.8
V
V
μ
A
V
V
ns
V
IL
V
IH
, V
CC
= 5 V
3.0
CE
IN
Pullup Current
CE
OUT
Output Voltage
3
0.4
I
SINK
= 1.6 mA
I
SOURCE
= 800
μ
A
V
CC
– 0.5
CE
Propagation Delay
5
25
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Frequency with Ext. Capacitor
±
2
5
μ
A
μ
A
kHz
kHz
0
250
OSC SEL = 0 V
OSC SEL = 0 V, C
OSC
= 47 pF
4
NOTE
1
WDI is a three-level input which is internally biased to 38% of V
CC
and has an input impedance of approximately 125 k
.
Specifications subject to change without notice.
REV. 0
–2–
(V
CC
= Full Operating Range, V
BATT
= +2.8 V, T
A
= T
MIN
to T
MAX
unless otherwise noted.)
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