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參數(shù)資料
| 型號： | ADM696AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuits |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 407K |
| 代理商： | ADM696AN |
ADM696/ADM697
REV. 0
–9–
APPLICATIONS INFORMATION
Increasing the Drive Current (ADM696)
If the continuous output current requirements at V
OUT
exceeds
100 mA or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM696)
can directly drive the base of the external transistor.
V
OUT
V
CC
BATTERY
+5V
INPUT
POWER
0.1μF
BATT
ON
V
BATT
PNP TRANSISTOR
ADM696
0.1μF
Figure 14. Increasing the Drive Current
Using a Rechargeable Battery for Backup (ADM696)
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
OUT
since this
eliminates the discharge path that would exist during power-
down if the resistor is connected to V
CC
.
V
OUT
V
CC
RECHARGABLE
BATTERY
+5V
INPUT
POWER
0.1μF
0.1μF
V
BATT
ADM696
R
I =
V
OUT
– V
BATT
R
Figure 15. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Fig-
ure 16. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 source current into the PFI summing
junction. This results in differing trip levels for the comparator.
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 17a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
ADM69x
R2
1.3V
PFO
R1
7805
R4
R3
+7V TO +15V
INPUT
POWER
+5V
PFI
V
CC
TO
μP NMI
V
H
= 1.3V
(
1+ R
)
V
L
= 1.3V
(
1+ R
)
R
2
ASSUMING R
4 < <
R
3
THEN
HYSTERESIS V
H
– V
L
= 5V
(
R
)
1
R
2
R
1
R
3
1
1
R
2
R
1
(5V – 1.3V)
1.3V (R
3 +
R
4
)
Figure 16. Adding Hysteresis to the Power Fail Comparator
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 17b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01
μ
F capacitor sets a watchdog timeout
delay of 100 s. When the control input is low, the OSC SEL pin
is driven high, selecting the internal oscillator. The 100 ms or
the 1.6 s period is chosen, depending on which diode in Fig-
ure 17b is used. With D1 inserted, the internal timeout is set at
100 ms while with D2 inserted the timeout is set at 1.6 s.
WDI
ADM69x
WATCHDOG
STROBE
CONTROL
INPUT
Figure 17a. Programming the Watchdog Input
OSC IN
OSC SEL
ADM69x
CONTROL
INPUT*
D1
D2
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 17b. Programming the Watchdog Input
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