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| 型號： | ADM6711TAKS |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PHOTO TRANSISTOR, NPN, SILICON; Channels, No. of:1; Output type:Transistor; Current, input:50mA; Voltage, output max:70V; Case style:3-TO-18; Mounting type:Through Hole RoHS Compliant: Yes |
| 中文描述： | 微處理器監(jiān)控電路4引腳SC70 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 155K |
| 代理商： | ADM6711TAKS |
REV. 0
–2–
ADM6711/ADM6713–SPECIFICATIONS
for L/M, 3.3 V for T/S, 3 V for R, and 2.5 V for Z models; unless otherwise noted.)
Parameter
CC
= Full Operating Range; T
A
= T
MIN
to T
MAX
; V
CC
Typ = 5 V
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
V
CC
Operating Voltage Range
1.0
1.2
5.5
5.5
35
V
V
μ
A
T
A
= 0
°
C to 70
°
C
T
A
= –40
°
C to +125
°
C
V
CC
< 5.5 V, ADM671_L/M,
T
A
= –40
°
C to +85
°
C
V
CC
< 3.6 V, ADM671_R/S/T/Z,
T
A
= –40
°
C to +85
°
C
V
CC
< 5.5 V, ADM671_L/M,
T
A
= 85
°
C to 125
°
C
V
CC
< 3.6 V, ADM671_R/S/T/Z,
T
A
= 85
°
C to 125
°
C
Supply Current
16
12
30
μ
A
60
μ
A
60
μ
A
RESET VOLTAGE THRESHOLD
ADM671_L
4.56
4.50
4.44
4.31
4.25
4.20
3.04
3.00
2.95
2.89
2.85
2.81
2.59
2.55
2.52
2.28
2.25
2.22
4.63
4.70
4.75
4.82
4.45
4.50
4.56
3.11
3.15
3.21
2.96
3.00
3.05
2.66
2.70
2.74
2.35
2.38
2.42
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T
A
= 25
°
C
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
T
A
= 25
°
C
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
T
A
= 25
°
C
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
T
A
= 25
°
C
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
T
A
= 25
°
C
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
T
A
= 25
°
C
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
ADM671_M
4.38
ADM671_T
3.08
ADM671_S
2.93
ADM671_R
2.63
ADM671_Z
2.32
RESET THRESHOLD TEMPERATURE
COEFFICIENT
30
ppm/
°
C
μ
s
V
CC
to
RESET
DELAY
RESET
ACTIVE TIMEOUT PERIOD
20
V
CC
= V
TH
to (V
TH
– 100 mV)
T
A
= –40
°
C to +85
°
C
T
A
= 85
°
C to 125
°
C
140
100
240
460
640
ms
ms
RESET
OUTPUT VOLTAGE
Low (ADM6711/ADM6713)
0.3
V
V
CC
= V
TH
min, I
SINK
= 1.2 mA,
ADM671_R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2 mA,
ADM671_L/M
V
CC
>1.0 V, I
SINK
= 50
μ
A
V
CC
> V
TH
max, I
SOURCE
= 500
μ
A,
ADM6711R/S/T/Z
V
CC
> V
TH
max, I
SOURCE
= 800
μ
A,
ADM6711L/M
0.4
V
0.3
V
V
High (ADM6711)
0.8 V
CC
0.8 V
CC
V
RESET
OPEN-DRAIN OUTPUT
LEAKAGE CURRENT
1
μ
A
V
CC
> V
TH
,
RESET
deasserted
MANUAL RESET (
MR
)
Input Threshold
0.3 V
CC
V
V
k
μ
s
ns
ns
V
IL
V
IH
0.7 V
CC
Pull-Up Resistance
Minimum Pulsewidth
Glitch Immunity
Reset Delay
10
1
20
100
200
Specifications subject to change without notice.
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