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參數(shù)資料
| 型號(hào)： | ADM489ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX RS-485 DIFF LP 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
ADM488/ADM489
Rev. D | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VCC 1
RO 2
DI 3
GND 4
A
8
B
7
Z
6
Y
5
ADM488
TOP VIEW
(Not to Scale)
00
07
9-
00
3
Figure 3. ADM488 8-Lead PDIP/SOIC Pin Configuration
Table 4. ADM488 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCC
Power Supply, 5 V ± 10%.
2
RO
Receiver Output. When A > B by 200 mV, RO = high. If A < B by 200 mV, RO = low.
3
DI
Driver Input. A logic low on DI forces Y low and Z high, while a logic high on DI forces Y high and Z low.
4
GND
Ground Connection, 0 V.
5
Y
Noninverting Driver, Output Y.
6
Z
Inverting Driver, Output Z.
7
B
Inverting Receiver, Input B.
8
A
Noninverting Receiver, Input A.
NC 1
RO 2
RE 3
DE 4
VCC
14
NC
13
A
12
B
11
DI 5
GND 6
GND 7
Z
10
Y
9
NC
8
NC = NO CONNECT
ADM489
TOP VIEW
(Not to Scale)
00
07
9-
00
4
Figure 4. ADM489 14-Lead PDIP/SOIC Pin Configuration
1
2
3
4
5
6
7
8
NC = NO CONNECT
16
15
14
13
12
11
10
9
NC
RO
RE
GND
DI
DE
VCC
A
B
NC
GND
NC
Y
Z
NC
ADM489
TOP VIEW
(Not to Scale)
00
07
9-
0
05
Figure 5. ADM489 16-Lead TSSOP Pin Configuration
Table 5. ADM489 Pin Function Descriptions
PDIP/SOIC
Pin No.
TSSOP
Pin No.
Mnemonic
Description
1, 8, 13
2, 9, 10, 13,
16
NC
No Connect. No connections are required to this pin.
2
3
RO
Receiver Output. When enabled, if A > B by 200 mV then RO = high. If A < B by 200 mV then
RO = low.
3
4
RE
Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a
high impedance state.
4
5
DE
Driver Output Enable. A high level enables the driver differential outputs, Y and Z. A low level
places it in a high impedance state.
5
6
DI
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, while a logic
high on DI forces Y high and Z low.
6, 7
7, 8
GND
Ground Connection, 0 V.
9
11
Y
Noninverting Driver, Output Y.
10
12
Z
Inverting Driver, Output Z.
11
14
B
Inverting Receiver, Input B.
12
15
A
Noninverting Receiver, Input A.
14
1
VCC
Power Supply, 5 V ± 10%.
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