參數(shù)資料
型號: ADM489AR
廠商: ANALOG DEVICES INC
元件分類: 通用總線功能
英文描述: Full-Duplex, Low Power, Slew Rate Limited, EIA RS-485 Transceivers
中文描述: LINE TRANSCEIVER, PDSO14
封裝: MS-012AB, SOIC-14
文件頁數(shù): 2/12頁
文件大小: 212K
代理商: ADM489AR
–2–
REV. 0
ADM488/ADM489–SPECIFICATIONS
Parameter
(V
CC
= +5 V
6
10%. All specifications T
MN
to T
MAX
unless
otherwse noted)
Min
T yp
Max
Units
T est Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
V
V
V
V
V
V
V
mA
mA
V
V
μ
A
R =
, Figure 1
V
CC
= 5 V, R = 50
(RS-422), Figure 1
R = 27
(RS-485), Figure 1
V
T ST
= –7 V to +12 V, Figure 2, V
CC
= 5 V
±
5%
R = 27
or 50
, Figure 1
R = 27
or 50
, Figure 1
R = 27
or 50
–7 V
V
O
+12 V
–7 V
V
O
+12 V
2.0
1.5
1.5
|V
OD
| for Complementary Output States
Common-Mode Output Voltage V
OC
|V
OC
| for Complementary Output States
Output Short Circuit Current (V
OUT
= High)
Output Short Circuit Current (V
OUT
= Low)
CMOS Input Logic T hreshold Low, V
INL
CMOS Input Logic T hreshold High, V
INH
Logic Input Current (DE, DI)
1.4
1.4
2.0
±
1.0
RECEIVER
Differential Input T hreshold Voltage, V
T H
Input Voltage Hysteresis,
V
T H
Input Resistance
Input Current (A, B)
–0.2
+0.2
V
mV
k
mA
mA
μ
A
V
V
mA
μ
A
–7 V
V
CM
+12 V
V
CM
= 0 V
–7 V
V
CM
+12 V
V
IN
= 12 V
V
IN
= –7 V
70
12
+1
–0.8
±
1
0.4
Logic Enable Input Current (
RE
)
CMOS Output Voltage Low, V
OL
CMOS Output Voltage High, V
OH
Short Circuit Output Current
T hree-State Output Leakage Current
I
OUT
= +4.0 mA
I
OUT
= –4.0 mA
V
OUT
= GND or V
CC
0.4 V
V
OUT
+2.4 V
4.0
7
85
±
1.0
POWER SUPPLY CURRENT
I
CC
Outputs Unloaded, Receivers Enabled
DE = 0 V (Disabled)
DE = 5 V (Enabled)
30
37
60
74
μ
A
μ
A
Specifications subject to change without notice.
TIMNGSPECIFICATIONS
Parameter
Min
T yp
Max
Units
T est Conditions/Comments
DRIVER
Propagation Delay Input to Output T
PLH
, T
PHL
Driver O/P to
O/P
T
SK EW
Driver Rise/Fall T ime T
R
, T
F
Driver Enable to Output Valid
Driver Disable T iming
Data Rate
250
2000
800
2000
2000
3000
ns
ns
ns
ns
ns
kbps
R
L
Diff = 54
, C
L1
= C
L2
= 100 pF, Figure 5
R
L
Diff = 54
, C
L1
= C
L2
= 100 pF, Figure 5
R
L
Diff = 54
, C
L1
= C
L2
= 100 pF, Figure 5
R
L
= 500
, C
L
= 100 pF, Figure 2
R
L
= 500
, C
L
= 15 pF, Figure 2
100
250
250
300
250
RECEIVER
Propagation Delay Input to Output T
PLH
, T
PHL
Skew |T
PLH
–T
PHL
|
Receiver Enable T
EN1
Receiver Disable T
EN2
Data Rate
250
2000
ns
ns
ns
ns
kbps
C
L
= 15 pF, Figure 5
100
10
10
50
50
R
L
= 1 k
, C
L
= 15 pF, Figure 4
R
L
= 1 k
, C
L
= 15 pF, Figure 4
250
Specifications subject to change without notice.
(V
CC
= +5 V
6
10%. All specifications T
MN
to T
MAX
unless otherwse noted)
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