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參數(shù)資料
型號: ADM4852ARZ
廠商: Analog Devices Inc
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC TXRX RS-485422 2.5MBPS 8-SOIC
標準包裝: 98
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 管件
產(chǎn)品目錄頁面: 790 (CN2011-ZH PDF)
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO 1
VCC
8
DI 4
GND
5
ADM4851/
ADM4852/
ADM4853
TOP VIEW
(Not to Scale)
RE 2
B
7
04931-002
DE
A
6
3
PIN 1
INDICATOR
NOTES
1. THE EXPOSED PADDLE ON THE UNDERSIDE
OF THE PACKAGE SHOULD BE SOLDERED
TO THE GROUND PLANE TO INCREASE THE
RELIABILITY OF THE SOLDER JOINTS AND
TO MAXIMIZE THE THERMAL CAPABILITY OF
THE PACKAGE.
1
RO
2
RE
3
DE
4
DI
7B
8VCC
TOP VIEW
(Not to Scale)
ADM4850/ADM4851/
ADM4852/ADM4853
6A
5GND
04
93
1-
0
29
Figure 3. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration,
SOIC and MSOP
Figure 4. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration, LFCSP
Pin No.
Mnemonic
Description
1
RO
Receiver Output. When RO is enabled, if (A B) ≥ 30 mV, RO = high; if (A B) ≤ 200 mV, RO = low.
2
RE
Receiver Output Enable. A low level on this pin enables the receiver output, RO. A high level places RO
into a high impedance state.
3
DE
Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level
places them into a high impedance state.
4
DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high
on DI forces A high and B low.
5
GND
Ground.
6
A
Noninverting Receiver Input A/Noninverting Driver Output A.
7
B
Inverting Receiver Input B/Inverting Driver Output B.
8
VCC
5 V Power Supply.
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相關代理商/技術參數(shù)
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