Data Sheet 
ADM4210
 
Rev. A | Page 13 of 16 
CIRCUIT BREAKER TIMING CYCLE 
When the voltage across the sense resistor exceeds the circuit 
breaker trip voltage, the 60 糀 timer pull-up current is activated. 
If the sense voltage falls below this level before the TIMER pin 
reaches 1.3 V, the 60 糀 pull-up is disabled and the 2 糀 pull-
down is enabled. This is likely to happen if the overcurrent fault 
is only transient, such as an inrush current. This is shown in 
Figure 31. However, if the overcurrent condition is continuous 
and the sense voltage remains above the circuit breaker trip 
voltage, the 60 糀 pull-up remains active. This allows the TIMER 
pin to reach the high trip point of 1.3 V and initiate the GATE 
shutdown. On the ADM4210-2, the TIMER pin continues pulling 
up but switches to the 5 糀 pull-up when it reaches the 1.3 V 
threshold. The device can be reset by toggling the ON-CLR
 pin 
or by manually pulling the TIMER pin low. On the ADM4210-1, 
the TIMER pin activates the 2 糀 pull-down once the 1.3 V 
threshold is reached, and continues to pull down until it reaches 
the 0.2 V threshold. At this point, the 100 糀 pull-down is 
activated and the GATE pin is enabled. The device keeps 
retrying in the manner as shown in Figure 32. 
The duty cycle of this automatic retry cycle is set to the ratio of 
2 糀/60 糀, which approximates 3.8% on. The value of the 
timer capacitor determines the on time of this cycle. This time 
is calculated as follows: 
t
ON
 = 1.3 ?C
TIMER
/60 糀  
t
OFF
 = 1.1 ?C
TIMER
/2 糀  
2礎(chǔ)
COMP1
COMP2
SHORT-
CIRCUIT
EVENT
60礎(chǔ)
100礎(chǔ)
V
TIMER
V
OUT
V
GSFET
I
RSENSE
FAULT
CYCLE
FAULT
CYCLE
 
Figure 32. ADM4210-1 Automatic Retry During Overcurrent Fault 
AUTOMATIC RETRY OR LATCHED OFF 
The ADM4210 is available in two models. The ADM4210-1 
has an automatic retry system whereby when a current fault is 
detected, the FET is shut down after a time determined by the 
timer capacitor, and it is switched on again in a controlled con-
tinuous cycle to determine if the fault remains (see Figure 32  
for details). The period of this cycle is determined by the timer 
capacitor at a duty cycle of 3.8% on and 96.2% off.  
The ADM4210-2 model has a latch off system whereby when a 
current fault is detected, the GATE is switched off after a time 
determined by the timer capacitor (see Figure 33 for details). 
Toggling the ON-CLR
 pin, or pulling the TIMER pin to GND 
for a brief period, resets this condition.  
5礎(chǔ)
COMP2
SHORT-
CIRCUIT
EVENT
60礎(chǔ)
V
TIMER
V
OUT
V
GSFET
I
RSENSE
 
Figure 33. ADM4210-2 Latch Off After Overcurrent Fault