
REV. B
–2–
ADM1486–SPECIFICATIONS
(V
CC
= +5 V ± 5%. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
5.0
5.0
5.0
5.0
0.2
3
0.2
150
150
0.8
V
V
V
V
V
V
V
mA
mA
V
V
μA
R = Infinity, Figure 1
V
CC
= 5 V, R = 50
R = 27
(RS-485), Figure 1
V
TST
= –7 V to +12 V, Figure 2
R = 27
or 50
R = 27
or 50
R = 27 or 50
–7 V
V
O
+12 V
–7 V
V
O
+12 V
2.0
2.1
2.1
(RS-422), Figure 1
V
OD3
|V
OD
| for Complementary Output States
Common-Mode Output Voltage V
OC
|V
OD
| for Complementary Output States
Output Short Circuit Current(V
OUT
=High) 60
Output Short Circuit Current(V
OUT
=Low)
CMOS Input Logic Threshold Low, V
INL
CMOS Input Logic Threshold High, V
INH
2.0
Logic Input Current (DE, DI)
, Figure 1
, Figure 1
60
±1.0
RECEIVER
Differential Input Threshold Voltage, V
TH
Input Voltage Hysteresis,
Input Resistance
Input Current (A, B)
–0.2
+0.2
V
mV
k
mA
mA
μA
V
V
mA
μA
–7 V
V
CM
= 0 V
–7 V
V
IN
= 12 V
V
IN
= –7 V
V
CM
+12 V
V
TH
70
20
V
CM
+12 V
+ 1
–0.8
±1
0.4
Logic Enable Input Current (
RE
)
CMOS Output Voltage Low, V
OL
CMOS Output Voltage High, V
OH
Short Circuit Output Current
Tristate Output Leakage Current
I
OUT
= +4.0 mA
I
OUT
= –4.0 mA
V
OUT
= GND or V
CC
0.4 V
V
OUT
4.0
7
85
±1.0
+2.4 V
POWER SUPPLY CURRENT
I
CC
(Outputs Enabled)
I
CC
(Outputs Disabled)
1.2
0.9
2.0
1.5
mA
mA
Outputs Unloaded, Digital Inputs = GND or V
CC
Outputs Unloaded, Digital Inputs = GND or V
CC
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(V
CC
= +5 V ± 5%. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Propagation Delay Input to Output T
PLH
, T
PHL
Driver O/P to
O/P
T
SKEW
Driver Rise/Fall Time T
R
, T
F
Driver Enable to Output Valid
Driver Disable Timing
4
8
0
5
8
8
15
2
10
15
15
ns
ns
ns
ns
ns
R
L
Diff = 54 C
L1
= C
L2
= 100 pF, Figure 3
R
L
Diff = 54 C
L1
= C
L2
= 100 pF, Figure 3
R
L
Diff = 54 C
L1
= C
L2
= 100 pF, Figure 3
RECEIVER
Propagation Delay Input to Output T
PLH
, T
PHL
Skew |T
PLH
–T
PHL
|
Receiver Enable T
EN1
Receiver Disable T
EN2
8
0
5
5
12
2
10
10
20
ns
ns
ns
ns
C
L
= 15 pF, Figure 5
Figure 6
Figure 6
Specifications subject to change without notice.
PRELIMINARY TECHNICAL DATA