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參數(shù)資料
| 型號(hào)： | ADM1172 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 2.7 V to 16.5 V Hot Swap Controller with Power-Fail Comparator |
| 中文描述： | 2.7 V至16.5 V熱風(fēng)熱插拔控制器與電源失效比較 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | ADM1172 |
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ADM1172
THEORY OF OPERATION
Many systems require the insertion or removal of circuit boards
to live backplanes. During this event, the supply bypass and hold-
up capacitors can require substantial transient currents from the
backplane power supply as they charge. These currents can
cause permanent damage to connector pins or undesirable glitches
and resets to the system.
Rev. 0 | Page 12 of 16
The ADM1172 is intended to control the powering of a system
(on and off) in a controlled manner, allowing the board to be
removed from, or inserted into, a live backplane by protecting it
from excess currents. The ADM1172 can reside either on the
backplane or on the removable board.
OVERVIEW
The ADM1172 operates over a supply range of 2.7 V to 16.5 V.
As the supply voltage is coming up, an undervoltage lockout
circuit checks if sufficient supply voltage is present for proper
operation. During this period, the FET is held off by the GATE
pin being held to GND. When the supply voltage reaches a level
above UVLO and the ON (ON-CLR) pin is high, an initial timing
cycle ensures that the board is fully inserted in the backplane
before turning on the FET. The TIMER pin capacitor sets the
periods for all of the TIMER pin functions. After the initial
timing cycle, the ADM1172 monitors the inrush current
through an external sense resistor. Overcurrent conditions are
actively limited to 50 mV/R
SENSE
for the circuit breaker timer
limit. The ADM1172-1 automatically retries after a current
limit fault and the ADM1172-2 latches off. The retry duty cycle
on the ADM1172-1 timer function is limited to 3.8% for FET
cooling.
UVLO
If the V
CC
supply is too low for normal operation, an under-
voltage lockout circuit holds the ADM1172 in reset. The GATE
pin is held to GND during this period. When the supply reaches
this UVLO voltage, the ADM1172 starts when the ON (ON-CLR)
pin condition is satisfied.
ON (ON-CLR) PIN
The ON (ON-CLR) pin is the enable pin. It is connected to a
comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM1172 is reset when the
ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is high,
the ADM1172 is enabled. A rising edge on this pin has the
added function of clearing a fault and restarting the device on
the latched off model, the ADM1172-2. A low input on the ON
(ON-CLR) pin turns off the external FET by pulling the GATE
pin to ground and resets the timer. An external resistor divider at
the ON (ON-CLR) pin can be used to program an undervoltage
lockout value higher than the internal UVLO circuit. There is a
glitch filter delay of approximately 3 μs on rising allowing the
addition of an RC filter at the ON (ON-CLR) pin to increase the
delay time at card insertion. If using a short pin system to
enable the device, a pull-down resistor should be used to hold
the device prior to insertion.
GATE
Gate drive for the external N-channel MOSFET is achieved
using an internal charge pump. The gate driver consists of a
12 μA pull-up from the internal charge pump. There are various
pull-down devices on this pin. At a hotswap condition the board
is hot inserted to the supply bus. During this event, it is possible
for the external FET GATE capacitance to be charged up by the
sudden presence of the supply voltage. This can cause
uncontrolled inrush currents. An internal strong pull-down
circuit holds GATE low while in UVLO. This reduces current
surges at insertion. After the initial timing cycle, the GATE is
then pulled high. During an overcurrent condition, the
ADM1172 servos the GATE pin in an attempt to maintain a
constant current to the load until the circuit breaker timeout
completes. In the event of a timeout, the GATE pin abruptly
shuts down using the 4 mA pull-down device. Care must be
taken not to load the GATE pin resistively because this reduces
the gate drive capability.
CURRENT LIMIT FUNCTION
The ADM1172 features a fast response current control loop that
actively limits the current by reducing the gate voltage of the
external FET. This current is measured by monitoring the
voltage drop across an external sense resistor. The ADM1172
tries to regulate the gate of the FET to achieve a 50 mV voltage
drop across the sense resistor.
CALCULATING THE CURRENT LIMIT
The sense resistor connected between V
CC
and the SENSE pin is
used to determine the nominal fault current limit. This is given
by the following equation:
ILIMIT
NOM
=
VCB
NOM
/
RSENSE
NOM
(1)
The minimum load current is given by Equation 2
ILIMIT
MIN
=
VCB
MIN
/RSENSE
MAX
(2)
The maximum load current is given by Equation 3.
ILIMIT
MAX
=
VCB
MAX
/
RSENSE
MIN
(3)
For proper operation, the minimum current limit must exceed
the circuit maximum operating load current with margin. The
sense resistor power rating must exceed
(
VCB
MAX
)
2
/
RSENSE
MIN
CIRCUIT BREAKER FUNCTION
When the supply experiences a sudden current surge, such as a
low impedance fault on load, the bus supply voltage can drop
significantly to a point where the power to an adjacent card is
affected, potentially causing system malfunctions. The
ADM1172 limits the current drawn by the fault by reducing the
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