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參數(shù)資料
| 型號(hào)： | ADM1069ACP-REEL7 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SUPER SEQUENCER-TM WITH MARGINING CONTROL AND AUXILIARY ADC INPUTS |
| 中文描述： | 超時(shí)序與裕度控制以及輔助ADC輸入商標(biāo) |
| 文件頁(yè)數(shù)： | 5/32頁(yè) |
| 文件大?。?/td> | 626K |
| 代理商： | ADM1069ACP-REEL7 |
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Preliminary Technical Data
ADM1069
Parameter
Conversion Time
Offset Error
Input Noise
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
Rev. PrB | Page 5 of 32
Min
Typ
0.44
84
0.25
8
Max
±2
Unit
ms
ms
LSB
LSB
rms
Bits
Test Conditions/Comments
One conversion on one channel
All 8 channels selected, 16x averaging enabled
V
REFIN
= 2.048 V
Direct input (no attenuator)
4 DACs are individually selectable for centering on
one of four output voltage ranges
Same range, independent of center point
Endpoint corrected
Sourcing Current, I
REFOUTMA X
= -200μA
Sinking Current, I
REFOUTMA X
= 100μA
Per mA
DC
100 mV step in 20 ns with 50 pF load
No load
Sourcing current, I
DACnMAX
= 100 μA
Sinking current, I
DACnMAX
= 100 μA
Capacitor required for decoupling, stability
Per 100 μA
DC
I
OH
= 0
I
OH
= 1μA
2 V < V
OH
< 7 V
V
PU
(pull-up to VDDCAP or V
PN
) = 2.7 V, I
OH
= 0.5 mA
V
PU
to V
pn
= 6.0 V, I
OH
= 0 mA
V
PU
≤ 2.7 V, I
OH
= 0.5 mA
I
OL
= 20 mA
Maximum sink current per PDO pin
Maximum total sink for all PDOs
Internal pull-up
Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
V
PDO
= 14.4 V
All on-chip time delays derived from this clock
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Load Regulation
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
PSRR
0.592
0.796
0.996
1.246
2.043
1
11
10.5
2.4
V
PU
0.3
0
0.6
0.8
1
1.25
601.25
2.36
-4
2
2.5
60
40
2.048
0.25
0.25
2
60
500
12.5
12
20
20
0.603
0.803
1.003
1.253
±0.75
±0.4
1
50
2
2.053
14
13.5
4.5
0.50
20
60
2
V
V
V
V
mV
mV
LSB
LSB
%
mV
mV
pF
μs
mV
dB
dB
V
mV
mV
μF
mV
dB
k
V
V
μA
V
V
V
V
mA
mA
k
mA
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
Load Regulation
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
V
OH
I
OUTAVG
Standard (Digital Output) Mode (PDO1–8)
V
OH
V
OL
I
OL2
I
SINK
2
R
PULL-UP
I
SOURCE
(VPn)
2
Three-State Output Leakage Current
Oscillator Frequency
90
100
10
110
μA
kHz
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