參數(shù)資料
型號(hào): ADM1065ASU-REEL7
廠商: ANALOG DEVICES INC
元件分類: 電源管理
英文描述: Super Sequencer-TM and Monitor
中文描述: 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝: 7 X 7 MM, PLASTIC, MS-026ABC, TQFP-48
文件頁(yè)數(shù): 4/28頁(yè)
文件大?。?/td> 497K
代理商: ADM1065ASU-REEL7
ADM1065
SPECIFICATIONS
VH = 3.0 V to 14.4 V
1
, VPn = 3.0 V to 6.0 V
1
, T
A
= 40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPn
VP
VH
VDDCAP
C
VDDCAP
POWER SUPPLY
Supply Current, I
VH
, I
VPn
Additional Currents
All PDO FET Drivers On
Rev. 0 | Page 4 of 28
Min
3.0
2.7
10
Typ
4.75
4.2
1
Max
6.0
14.4
5.4
6
Unit
V
V
V
V
μF
mA
mA
Test Conditions/Comments
Minimum supply required on one of VPn, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1–10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1–6 loaded with 1 μA each,
PDO7–10 off
Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP
6 DACs on with 100 μA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset
error + input attenuation error
Minimum programmable filter length
Maximum programmable filter length
No load
Sourcing current, I
DACnMAX
= 100 μA
Sinking current, I
DACnMAX
= 100 μA
Capacitor required for decoupling, stability
Per 100 μA
DC
Current Available from VDDCAP
2
mA
DACs Supply Current
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPn Pins
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VX Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
6
2.5
2.5
1.25
0.573
1
0.573
2.2
1
10
±0.05
±0.05
14.4
6
6
3
1.375
1.375
±1
mA
mA
mA
%
V
V
%
V
V
V
M
V
%
Threshold Resolution
Digital Glitch Filter
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
Load Regulation
PSRR
2.043
1
8
0
100
2.048
0.25
0.25
2
60
2.053
Bits
μs
μs
V
mV
mV
μF
mV
dB
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