參數(shù)資料
型號: ADM1033ARQZ-RL7
廠商: ON Semiconductor
文件頁數(shù): 20/35頁
文件大?。?/td> 424K
描述: IC THERM/FAN SPEED CTLR 16-QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
Product Discontinuation 30/Sept/2011
標(biāo)準(zhǔn)包裝: 1,000
功能: 風(fēng)扇控制,溫度監(jiān)控器
傳感器類型: 內(nèi)部和外部
感應(yīng)溫度: -40°C ~ 125°C,外部傳感器
精確度: ±1°C
拓?fù)洌?/td> ADC,比較器,多路復(fù)用器,寄存器庫
輸出類型: SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
ADM1033
http://onsemi.com
20
THERM
 % Exceeded Bit (Bit 4) in Status Register 2 (Address
0x50) is asserted and an ALERT
 is generated, that is, if the
mask bit is not set. If the limit is set to 0x00, an ALERT
 is
generated on the first assertion. If the limit is set to 0xFF, an
ALERT
 is never generated. This is because 0xFF corresponds
to the THERM
 input, which is asserted continuously.
Table 25. CONVERSION RATES
Code
THERM
 %
On-Time Window
000
0.25 s
001
0.5 s
010
1 s
011
2 s
100
4 s
101
8 s
110
8 s
111
8 s
When THERM
 is configured as an input only, setting the
Enable THERM
 Events bits in Configuration Register 4
allows Pin 7 to operate as an I/O.
The user can configure the THERM
 pin to be pulled low
as an output whenever the local temperature exceeds the
local THERM
  limit. To do this, set the Enable Local
THERM
  events bit (Bit 0) of Configuration Register 4
(Address 0x04).
The user can also configure the THERM
 pin to be pulled
low as an output whenever the Remote 1 temperature
exceeds the Remote 1 THERM
  limit. Set the Enable
Remote 1 THERM
  events bit (Bit 1) of Configuration
Register 4 (Address 0x04).
THERM
 % Limit Register
The THERM
 % limit is programmed to Register 0x19. An
ALERT
 is generated, if THERM
 is asserted for longer than
the programmed percentage limit. The limit is programmed
as a percentage of the chosen time window.
THERM
 % limit register is an 8-bit register.
0x00 = 0%
0xFF = 100%
Therefore, 1 LSB = 0.39%.
Example:
If a time window of 8 seconds is chosen, and an ALERT
is to be generated if THERM
 is asserted for more than
1 second, program the following value to the limit register:
% Limit = 1/8 ?100 = 12.5%
12.5%/0.39% = 32d = 0x20 = 0010 0000
An ALERT
 is generated if the THERM
 limit is exceeded
after the time window has elapsed, assuming it is not
masked.
Fan Drive Signal
The ADM1033 contols the speed of up to one cooling fan.
Varying the duty cycle (on/off time) of a square wave
applied to the fan varies the speed of the fan. The ADM1033
uses a control method called synchronous speed control, in
which the PWM drive signal applied to the fan is
synchronized with the fans TACH signal. See the
Synchronous Speed Control section for more information.
The external circuitry required to drive the fan is very
simple. A single N-channel MOSFET is the only drive
device required. The specifications of the MOSFET depend
on the maximum current required by the fan and the gate
voltage drive (V
GS
< 3.0 V for direct interfacing to the drive
pin). V
GS
 can be greater than 3.0 V, as long as the pullup on
the gate is tied to 5.0 V. The MOSFET should also have a low
on-resistance to ensure that there is no significant voltage
drop across the FET. A high on-resistance reduces the
voltage applied across the fan and therefore the maximum
operating speed of the fan. Figure 33 shows a scheme for
driving a 3-wire fan.
Figure 33. Interfacing a 3-wire Fan to the ADM1033
by Using an N-channel MOSFET
ADM1033
TACH
DRIVE
TACH
Q1
NDT3055L
12 V
FAN
3.3 V
12 V
12 V
10 kW
4.7 kW
100 kW
10 kW
Figure 33 uses a 10 kW pullup resistor for the TACH
signal. This assumes that the TACH signal is an open
collector from the fan. In all cases, the fans TACH signal
must be kept below 5.0 V maximum to prevent damaging
the ADM1033.
If in doubt as to whether a fan has an open-collector or
totem pole TACH output, use one of the input signal
conditioning circuits shown in the Fan Inputs section.
When designing drive circuits with transistors and FETs,
make sure that the drive pins are not required to source
current and that they sink less than the maximum current
specified here.
Synchronous Speed Control
The ADM1033 drives the fan by using a control scheme
called synchronous speed control. In this scheme, the PWM
drive signal applied to the fan is synchronized with the
TACH   signal.   Accurate   and   repeatable   fan   speed
measurements are the main benefits. The fan is allowed to
run reliably at speeds as low as 30 percent of the full
capability.
The drive signal applied to the fan is synchronized with
the TACH signal. The ADM1033 switches on the drive
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