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參數(shù)資料
| 型號： | ADM00398 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/17頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR 16BIT MCU MCP3911 |
| 設(shè)計資源： | MCP3911 Eval Brd Schematics ADM00398 BOM ADM00398 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MCP3911，PIC24FJ256GA110 |
| 所含物品： | 板，線纜 |
MCP3911
DS22286A-page 6
2012 Microchip Technology Inc.
1.2
SERIAL INTERFACE CHARACTERISTICS
TABLE 1-2:
SERIAL DC CHARACTERISTICS TABLE
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to
+125°C, CLOAD = 30pF, applies to all digital I/O.
Sym
Characteristics
Min
Typ
Max
Units
Test Conditions
VIH
High-level Input voltage
0.7 DVDD
—
V
Schmitt Triggered
VIL
Low-level Input voltage
—
0.3 DVDD
V
Schmitt Triggered
ILI
Input leakage current
—
±1
A
CS = DVDD, VIN = DGND TO
DVDD
ILO
Output leakage current
—
±1
A
CS = DVDD, VOUT = DGND OR
DVDD
VHYS
Hysteresis of Schmitt Trig-
ger Inputs
—200
mV
VOL
Low-level output
voltage
——
0.4
V
IOL = +2.1mA, DVDD = 3.3V
VOH
High-level output
voltage
DVDD -0.5
—
V
IOH = -2.1mA, DVDD = 3.3V
CINT
Internal capacitance
(all inputs and
outputs)
——
7
pF
TA = 25°C, SCK = 1.0 MHz,
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
TABLE 1-3:
SERIAL AC CHARACTERISTICS TABLE
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to
+125°C, GAIN = 1, CLOAD = 30pF.
Sym
Characteristics
Min
Typ
Max
Units
Test Conditions
fSCK
Serial Clock frequency
—
20
MHz
t
CSS
CS setup time
25
—
ns
t
CSH
CS hold time
50
—
ns
t
CSD
CS disable time
50
—
ns
tsu
Data setup time
5
—
ns
t
HD
Data hold time
10
—
ns
t
HI
Serial Clock high time
20
—
ns
t
LO
Serial Clock low time
20
—
ns
t
CLD
Serial Clock delay time
50
—
ns
t
CLE
Serial Clock enable time
50
—
ns
t
DO
Output valid from SCK low
—
25
ns
t
DOMDAT
Modulator output valid from
AMCLK high
——
1/(2*AMCLK)
s
t
HO
Output hold time
0
—
ns
t
DIS
Output disable time
—
25
ns
tMCLR
Reset Pulse Width (RESET)100
—
ns
tDODR
Data Transfer Time to DR
(Data Ready)
—25
ns
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
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