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參數(shù)資料
| 型號： | ADL5562ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP DIFF RF/IF 3.3GHZ 16LFCSP |
| 產(chǎn)品培訓模塊： | Differential Circuit Design Techniques for Communication Applications |
| 設計資源： | Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110) |
| 標準包裝： | 1 |
| 放大器類型： | RF/IF 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 轉換速率： | 9800 V/µs |
| -3db帶寬： | 3.3GHz |
| 電流 - 輸入偏壓： | 3µA |
| 電流 - 電源： | 80mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-VQ |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 其它名稱： | ADL5562ACPZ-R7DKR |
Data Sheet
ADL5562
Rev. E | Page 15 of 24
INPUT AND OUTPUT INTERFACING
The ADL5562 can be configured as a differential-input to
differential-output driver, as shown in Figure 34. The differential
broadband input is provided by the ETC1-1-13 balun transformer,
and the two 34.8 Ω resistors provide a 50 Ω input match for the
three input impedances that change with the variable gain
strapping. The input and output 0.1 F capacitors isolate the VCC/2
bias from the source and balanced load. The load should equal 200
to provide the expected ac performance (see the Specifications
section and the Typical Performance Characteristics section).
3.3V
VIP2
VIP1
VIN1
VIN2
A
B
50
AC
R2
08003-
043
+
0.1F
ETC1-1-13
0.1F
+
R1
+
0.1F
NOTES
1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
AND INPUT B TO BOTH VIN1 AND VIN2.
RL
2
RL
2
Figure 34. Differential-Input to Differential-Output Configuration
Table 4. Differential Termination Values for Figure 34
Gain (dB)
R1 ()
R2 ()
6
28.7
12
33.2
15.5
40.2
The differential gain of the ADL5562 is dependent on the
source impedance and load, as shown in Figure 35.
RL
200
400
400
200
100
100
VIP2
VIP1
VIN1
VIN2
5
5
08003-
044
+
0.1F
2
RL
2
AC
1/2 RS
0.1F
+
0.1F
+
Figure 35. Differential Input Loading Circuit
The differential gain can be determined using the following
formula. The values of RIN for each gain configuration are
shown in Table 5.
L
IN
V
R
A
+
×
=
10
400
(1)
Table 5. Values of RIN for Differential Gain
Gain (dB)
RIN ()
6
200
12
100
15.5
66.7
Single-Ended Input to Differential Output
The ADL5562 can also be configured in a single-ended input
to differential output driver, as shown in Figure 36. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 6 with the required terminations
to match to a 50 source using R1 and R2. Note that R1 must
equal the parallel value of the source and R2. The input and
output 0.1 F capacitors isolate the VCC/2 bias from the source
and the balanced load. The performance for this configuration
is shown in Figure 11, Figure 14, and Figure 20.
VIP2
VIP1
VIN1
VIN2
A
B
50
AC
R2
08003-
045
+
0.1F
3.3V
+
R1
NOTES
1. FOR 5.6dB GAIN (AV = 1.9), CONNECT INPUT A TO VIP1
AND INPUT B TO VIN1.
2. FOR 11.1dB GAIN (AV = 3.6), CONNECT INPUT A TO VIP2
AND INPUT B TO VIN2.
3. FOR 14.1dB GAIN (AV = 5.1), CONNECT INPUT A TO BOTH
VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
+
0.1F
RL
2
RL
2
Figure 36. Single-Ended Input to Differential Output Configuration
Table 6. Single-Ended Termination Values for Figure 36
Gain (dB)
R1 ()
R2 ()
5.6
27
60
11.1
29
69
14.1
30
77
The single-ended gain configuration of the ADL5562 is dependent
on the source impedance and load, as shown in Figure 37.
RL
200
400
400
200
100
100
VIP2
VIP1
VIN1
VIN2
5
5
RS
AC
R2
08003-
046
+
0.1F
+
R1
+
2
RL
2
Figure 37. Single-Ended Input Loading Circuit
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