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參數(shù)資料
| 型號(hào)： | ADL5531ACPZ-R71 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 20 MHz to 500 MHz IF Gain Block |
| 中文描述： | 20 MHz至500 MHz的中頻增益模塊 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 261K |
| 代理商： | ADL5531ACPZ-R71 |
ADL5531
BASIC CONNECTIONS
The basic connections for operating the ADL5531 are shown
in Figure 15. The input and output are ac-coupled with 10 nF
(0402) capacitors. DC bias is provided to the amplifier via an
inductor (Coilcraft 1008CS-471XJLC or equivalent) connected
to the RFOUT pin. The bias voltage should be decoupled using
10 nF and 1 μF capacitors.
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 14 shows the recommended land pattern for ADL5531.
To minimize thermal impedance, the exposed paddle on the
package underside is soldered down to a ground plane. If
multiple ground layers exist, they are stitched together using
vias (a minimum of five vias is recommended). Pin 1, Pin 3,
Pin 4, Pin 6 and Pin 8 can be left unconnected or can be
connected to ground. Connecting these pins to ground slightly
enhances thermal impedance. For more information on land
pattern design and layout, refer to Application Note AN-772,
A
Design and Manufacturing Guide for the Lead Frame Chip Scale
Package (LFCSP)
.
Rev. 0 | Page 9 of 12
0
1.53mm
0
1
1
2.03mm
4
5
8
0.71mm
1
Figure 14. Recommended Land Pattern
5
CLIN
8
NC
NC
NC = NO CONNECT
RFIN
RFOUT
L1
470nH
4
6
NC
RFIN
2
7
RFOUT
NC
3
NC
ADL5531
0
1
C1
10nF
C3
1nF
C5
10nF
C2
10nF
C6
1μF
VPOS
(TESTLOOP RED)
GND
(TESTLOOP BLACK)
W1
Figure 15. Basic Connections
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADL5531-EVALZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD ADL5531 |
| ADL5531-EVALZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:20 MHz to 500 MHz IF Gain Block |
| ADL5532 | 制造商:AD 制造商全稱:Analog Devices 功能描述:20 MHz to 500 MHz IF Gain Blocks |
| ADL5532ACPZ-R7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:20 MHz to 500 MHz IF Gain Blocks |
| ADL5532ACPZ-WP | 制造商:AD 制造商全稱:Analog Devices 功能描述:20 MHz to 500 MHz IF Gain Blocks |
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