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參數(shù)資料
| 型號： | ADL5391ACPZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | DC to 2.0 GHz Multiplier |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC16 |
| 封裝： | 3 X 3 MM, MO-220-VEED-2, LEAD FREE, LFCSP-16 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 394K |
| 代理商： | ADL5391ACPZ-R7 |
ADL5391
Rev. 0 | Page 12 of 16
0
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
10
100
200
300
400
500
600
700
800
900
1000
G
FREQUENCY (MHz)
BLEEDTHRU GAIN
SECOND HARMONIC GAIN
THIRD HARMONIC GAIN
0
Figure 18. Single-Ended (DC) ADL5391 Used as a Harmonic Generator
21
74
21
74
XIN
YIN
150
62
5dB PAD
5dB PAD
10dB PAD
53
53
200
XM
XP
YM
YP
WP
WM
0
Figure 19. Setup for Single-Ended Data
Use as a Detector
The ADL5391 can be used as a square law detector. When
amplitude squaring is performed, there are components of the
multiplier output that correlate to the signal bleedthrough and
second harmonic, as seen in Equation 4. However, as noted in
the Squaring and Frequency Doubling section, there is also a dc
component that is directly related to the offset and the squared
input magnitude. If a signal is split and feed into the X and Y
inputs and a low-pass filter were place on the output, the resulting
dc signal would be directly related to the square of the input
magnitude. The intercept of the response will shift slightly from
part to part (and over temperature) with the offset, but this can
be removed through calibration. Figure 20 shows the response
of the ADL5391 as a square law detector, Figure 21 shows the
error vs. the input power, and Figure 22 shows the
configuration used.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
O
V
IN
(V rms)
2
0
.8
Figure 20. ADL5391 Used as Square Law Detector DC Output vs. Square of Input
1.6
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–30
10
5
0
–5
–10
–15
–20
–25
E
PIN X (dBm)
0
Figure 21. ADL5391Used as a Square Law Detector Error vs. Power Input
0
T1
45nF
40μH
40μH
74μH
74μH
J2
WM
J1
WP
XM
XP
YM
YP
11
12
13
14
WP
WM
6
5
R2
56.2
TC1-1-13M
T3
C7
0.1μF
C18
0.1μF
J6
YP
R1
56.2
TC1-1-13M
T2
C4
0.1μF
C20
0.1μF
J8
XP
R4
100
R12
OPEN
40nF
R6
24.9
R5
24.9
Figure 22. Schematic for ADL5391 Used as Square Law Detector
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| ADL5391ACPZ-WP | DC to 2.0 GHz Multiplier |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADL5391ACPZ-WP | 制造商:Analog Devices 功能描述:ANLG MLTPLR 2-BIT 2GHZ 16LFCSP EP - Waffle Pack |
| ADL5391-EVAL | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| ADL5391-EVALZ | 制造商:Analog Devices 功能描述:EVAL BOARD DC-2GHZ MULTI ADL5391 制造商:Analog Devices 功能描述:ADL5391, MULTIPLIER, EVAL BOARD 制造商:Analog Devices 功能描述:ADL5391, MULTIPLIER, EVAL BOARD; Silicon Manufacturer:Analog Devices; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: Yes |
| ADL54054901 | 制造商:LG Corporation 功能描述:Evaporator Assembly,First |
| ADL55 | 制造商:Pentair Technical Products / Hoffman 功能描述:DRAW LATCH M55 (PKG 2) , 0.00x0.00x0.00, |
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