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| 型號： | ADL5304ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LOG CONV 32LFCSP |
| 標準包裝： | 5,000 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADL5304
Data Sheet
Rev. 0 | Page 22 of 32
09
45
9
-06
0
TEMPERATURE
COMPENSATION
26
1P5V
DCBI
27
1.5V
24
BIAS
INPS
INMS
VLOG
23
22
5k
7.5k
21
20
19
15
SCL1
SCL2
SCL3
ILOG
ACOM
Reference Outputs
The ADL5304 has three trimmed precision references, two
voltages, and one current (IREF). The voltages are 1.500 V and
2.000 V at the 1P5V and 2VLT pins, respectively. The 1P5V
reference is intended to provide the bias to the VSM1 to VSM4,
DCBI, and INPS pins; it can sink up to 10 mA and source a
maximum of about 5 mA.
The 2VLT reference can source up to 20 mA of current, but it
cannot sink any current. The primary use of the 2.0 V reference
is for photodiode bias, or to generate reference currents other
than the 100 nA provided by IREF. Together with a precision resistor,
the 1.5 V and 2.0 V references can reliably generate any current
up to approximately 5 mA.
The IREF current, nominally 100 nA, flows out of the IREF pin and
is primarily used as an input to the IDEN pin to provide the
denominator current, IDEN. The choice of 100 nA places it in the
middle of the 1 pA to 10 mA range. IREF can also be used as the
input to the INUM pin and thereby invert the basic log response of
Whereas if INUM = IREF and the input current is applied to IDEN,
VLOG decreases with increasing IDEN.
Figure 51. Buffer Amplifier in Default Configuration
The buffer amplifier is a voltage feedback op amp with supplies
between VPOS and VNEG. For single-supply operation, the
VNEG pin is tied to ground, and the INPS pin, the positive
input of the op amp, to the 1P5V pin.
If a ground referenced input is desired at the INUM or IDEN
pins, then the INPS and DCBI pins together with the VSMx
pins must be tied to ground, and VNEG needs to be less than
2 V. If larger slopes are required, VPOS can increase to +5 V,
and VNEG can increase to 5 V. For example, if the SCL3 pin is
connected to VLOG, and SCL1 and SCL2 remain open, the
internal 7.5 kΩ resistor, together with the 80 μA/decade ILOG,
provides a slope of 0.6 V/decade at the VLOG pin. Implementation
of slopes of 0.2 V/decade to 0.8 V/decade is easily
accomplished.
Buffer Amplifier
A buffer amplifier completes the signal chain that takes the ILOG
current from the temperature compensation block and converts
it to a voltage at the VLOG pin. The buffer amplifier gain and
offset can be configured to provide different logarithmic slope and
intercept at the VLOG output. On-chip resistors provide optimized
scale factors and intercepts via the SCL1, SCL2, and SCL3 pins.
For example, in Figure 51, the default setup provides a scale of
0.2 V/decade and an intercept of 3.162 fA. VOFS = VLOG = 1.5 V
when the internal ILOG = 0 A, which corresponds to INUM = IDEN. ILOG
varies from 400 μA to +400 μA with a scale of 80 μA/decade over
the full 200 dB input current range. In the default configuration,
ILOG is negative for INUM > IDEN and positive for INUM < IDEN. If the
input current is applied to the IDEN pin and the reference current
(IREF) to the INUM pin, the slope of VLOG is negative and the range
is inverted, that is, VLOG is 2.5 V for IDEN = 1 pA, and VLOG is 0.5 V
for IDEN = 10 mA.
Setting the Log Slope and Intercept
The choice of optimal slope and intercept depends on the
application and supply voltage(s). For example, when an input
current range of less than the full 200 dB is desired, a higher slope
can be chosen to better use the full voltage span available at
VLOG, and perhaps optimally position it to suit the input capacity
of a subsequent analog-to-digital converter (ADC). Very high
slopes, such as 0.8 V/decade, can be realized, allowing a smaller
range of IPD to be measured at high sensitivity.
Any other intercept and slope can be realized using external
resistors, but these do not, in general, form accurate ratios to
the on-chip resistors. Therefore, some inaccuracies should be
expected. If the SCL1, SCL2, and SCL3 pins are not connected
and a resistor is placed between the INMS and VLOG pins, the
ILOG current is forced through the external resistor and thereby
has a log slope that is 80 μA/decade times REXT; VOFS is equal to
the voltage applied to the INPS pin.
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