參數(shù)資料
型號(hào)： ADG793GBCPZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/24頁(yè)
文件大?。?/td> 0K
描述： IC MUX/DEMUX TRIPLE 3X1 24LFCSP
產(chǎn)品變化通告： ADG79xx Discontinuance Notice 17/Aug/2010
標(biāo)準(zhǔn)包裝： 1
功能： 多路復(fù)用器/多路分解器
電路： 3 x 3:1
導(dǎo)通狀態(tài)電阻： 4 歐姆
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3V，5V
電流 - 電源： 1nA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 801 (CN2011-ZH PDF)
其它名稱(chēng)： ADG793GBCPZ-REELDKR
ADG793A/ADG793G
Rev. 0 | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE TIED TO GND.
1
S1A
2
S1B
3
D1
4
NC
5
S1C
6
NC
15 D3
16 NC
17 S3C
18 A2
14 S3B
13 S3A
7
S
2A
8
S
2B
9
D
2
11
S
2C
12
N
C
10
N
C
21
S
C
L
22
S
D
A
23
V
D
24
G
N
D
20
A
0
19
A
1
ADG793A
TOP VIEW
(Not to Scale)
0
603
0-
029
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE TIED TO GND.
1
S1A
2
S1B
3
D1
4
NC
5
S1C
6
GPO2
15 D3
16 NC
17 S3C
18 A2
14 S3B
13 S3A
7
S
2A
8
S
2B
9
D
2
11
S
2C
12
G
P
O
1
10
N
C
21
S
C
L
22
S
D
A
23
V
D
24
G
N
D
20
A
0
19
A
1
ADG793G
TOP VIEW
(Not to Scale)
06
030
-0
30
Figure 3. ADG793A Pin Configuration
Figure 4. ADG793G Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
S1A
A-Side Source Terminal for Mux 1. Can be an input or output.
2
S1B
B-Side Source Terminal for Mux 1. Can be an input or output.
3
D1
Drain Terminal for Mux 1. Can be an input or output.
4
NC
Not internally connected.
5
S1C
C-Side Source Terminal for Mux 1. Can be an input or output.
6
NC/GPO2
Not internally connected for ADG793A. General-Purpose Logic Output 2 for ADG793G.
7
S2A
A-Side Source Terminal for Mux 2. Can be an input or output.
8
S2B
B-Side Source Terminal for Mux 2. Can be an input or output.
9
D2
Drain Terminal for Mux 2. Can be an input or output.
10
NC
Not internally connected.
11
S2C
C-Side Source Terminal for Mux 2. Can be an input or output.
12
NC/GPO1
Not internally connected for ADG793A. General-Purpose Logic Output 1 for ADG793G.
13
S3A
A-Side Source Terminal for Mux 3. Can be an input or output
14
S3B
B-Side Source Terminal for Mux 3. Can be an input or output.
15
D3
Drain Terminal for Mux 3. Can be an input or output.
16
NC
Not internally connected.
17
S3C
C-Side Source Terminal for Mux 3. Can be an input or output.
18
A2
Logic Input. Sets Bit A2 from the third least significant bit of the 7-bit slave address.
19
A1
Logic Input. Sets Bit A1 from the second least significant bit of the 7-bit slave address.
20
A0
Logic Input. Sets Bit A0 from the first least significant bit of the 7-bit slave address.
21
SCL
Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into
the device. External pull-up resistor required.
22
SDA
Digital I/O. Bidirectional open-drain data line. External pull-up resistor required.
23
VDD
Positive Power Supply Input.
24
GND
Ground (0 V) Reference.
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