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參數(shù)資料
| 型號： | ADG714 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, Low Voltage Serially-Controlled, Octal SPST Switches |
| 中文描述： | 的CMOS低電壓串行控制，八SPST開關 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 173K |
| 代理商： | ADG714 |
ADG714/ADG715
ADG715 TIMING CHARACTERISTICS
1
–6–
REV. 0
Parameter
Limit at T
MIN
, T
MAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
Unit
Conditions/Comments
f
SCL
t
1
t
2
t
3
t
4
t
5
t
62
kHz max
μ
s min
μ
s min
μ
s min
μ
s min
ns min
μ
s max
μ
s min
μ
s min
μ
s min
μ
s min
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD, STA
, Start/Repeated Start Condition Hold Time
t
SU, DAT
, Data Setup Time
t
HD, DAT
, Data Hold Time
t
7
t
8
t
9
t
SU, STA
, Setup Time for Repeated Start
t
SU, STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time Between a STOP Condition and
a Start Condition
t
R
, Rise Time of both SCL and SDA when Receiving
t
10
300
20 + 0.1C
b3
250
300
20 + 0.1C
b3
400
50
ns max
ns min
ns max
ns max
ns min
pF max
ns max
t
11
t
11
t
F
, Fall Time of SDA When Receiving
t
F
, Fall Time of SDA when Transmitting
C
b
t
SP4
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
NOTES
1
See Figure 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
SDA
SCL
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
8
t
1
t
7
t
4
t
5
t
11
t
2
t
6
t
10
t
3
t
4
t
9
Figure 2. 2-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications –40 C to +85 C unless otherwise noted.)
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| ADG714BRU | CMOS, Low Voltage Serially-Controlled, Octal SPST Switches |
| ADG715 | REC3-SRW_DRW/H* Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 15V; Power: 3W; 2kV, 4kVDC & 6kVDC Isolation; Industry Standard 3W DIP24 Package; Feedback Regulated Output; Continuous Short Circuit Protection; Wide Input 2:1 & 4:1; Medical Approvals (4kV/6kV Versions); EN and UL Certificates; 3 Pinout Options, 3 Case Styles; Control Pin Option; Efficiency to 86% |
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相關代理商/技術參數(shù) |
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|---|---|
| ADG714_02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, Low Voltage Serially Controlled, Octal SPST Switches |
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| ADG714BRU-REEL | 制造商:Analog Devices 功能描述:Analog Switch Octal SPST 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ANLG SW OCTAL SPST 5.5V 24TSSOP - Tape and Reel |
| ADG714BRU-REEL7 | 制造商:Analog Devices 功能描述:Analog Switch Octal SPST 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ANLG SW OCTAL SPST 5.5V 24TSSOP - Tape and Reel |
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