參數(shù)資料
型號(hào): ADG604YRU
廠(chǎng)商: ANALOG DEVICES INC
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: 1 pC Charge Injection, 100 pA Leakage CMOS 5 V/5 V/3 V 4-Channel Multiplexer
中文描述: 4-CHANNEL, SGL ENDED MULTIPLEXER, PDSO14
封裝: TSSOP-14
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 155K
代理商: ADG604YRU
REV. 0
ADG604
–6–
TERMINOLOGY
V
DD
V
SS
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground at the device.
Ground (0 V) Reference
Positive Supply Current
Negative Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Ohmic Resistance between D and S
On Resistance Match between any two channels, i.e., R
ON
Max – R
ON
Min
Flatness is defined as the difference between the maximum and minimum value of On resistance as measured
over the specified analog signal range.
Source Leakage Current with the Switch “OFF”
Drain Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Analog Voltage on Terminals D, S
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
Channel Input Capacitance for “OFF” Condition
Channel Output Capacitance for “OFF” Condition
“On” Switch Capacitance
Digital Input Capacitance
Delay time between the 50% and 90% points of the digital input and switch “ON” condition.
Delay time between the 50% and 90% points of the digital input and switch “OFF” condition.
Delay time between the 50% and 90% points of the digital input and switch “ON” condition when switching
from one address state to another.
“OFF” time or “ON” time measured between the 80% points of both switches, when switching from one address
state to another.
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.
A measure of unwanted signal coupling through an “On” switch.
Frequency Response of the “On” Switch
Loss Due to the On Resistance of the Switch
GND
I
DD
I
SS
S
D
R
ON
R
ON
R
FLAT(ON)
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
D
, V
S
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
(EN)
t
OFF
(EN)
t
TRANSITION
t
BBM
Charge Injection
Crosstalk
Off Isolation
Bandwidth
Insertion Loss
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