參數(shù)資料
型號: ADG453BR
廠商: ANALOG DEVICES INC
元件分類: 運(yùn)動控制電子
英文描述: LC2MOS 5 ohm RON SPST Switches
中文描述: QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16
封裝: MS-012AC, SOIC-16
文件頁數(shù): 8/12頁
文件大小: 161K
代理商: ADG453BR
ADG451/ADG452/ADG453
REV. A
–8–
FREQUENCY – Hz
1k
120
100
10k
100k
1M
10M
C
V
DD
=
1
15V
V
SS
= –15V
V
L
=
1
5V
R
LOAD
= 50
V
100
20
0
40
60
80
100M
Figure 9. Crosstalk vs. Frequency
200
100
10
–3.5
1
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
L
FREQUENCY – MHz
V
DD
=
1
15V
V
SS
= –15V
V
L
=
1
5V
Figure 10. Frequency Response with Switch On
APPLICAT ION
Figure 11 illustrates a precise, fast, sample-and-hold circuit.
An AD845 is used as the input buffer while the output
operational amplifier is an AD711. During the track mode,
SW1 is closed and the output V
OUT
follows the input signal
V
IN
. In the hold mode, SW1 is opened and the signal is
held by the hold capacitor C
H
.
ADG451/
452/453
AD845
AD711
+15V
+5V
SW2
S
S
D
D
SW1
+15V
V
IN
–15V
–15V
CH
2200pF
–15V
V
OUT
75
V
R
C
C
1000pF
+15V
2200pF
Figure 11. Fast, Accurate Sample-and-Hold Circuit
Due to switch and capacitor leakage, the voltage on the
hold capacitor will decrease with time. T he ADG451/
ADG452/ADG453 minimizes this droop due to its low
leakage specifications. T he droop rate is further minimized
by the use of a polystyrene hold capacitor. T he droop rate
for the circuit shown is typically 30
μ
V/
μ
s.
A second switch, SW2, that operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differ-
ential effect on the op amp AD711, which will minimize
charge injection effects. Pedestal error is also reduced by the
compensation network R
C
and C
C
. T his compensation net-
work reduces the hold time glitch while optimizing the ac-
quisition time. Using the illustrated op amps and component
values, the pedestal error has a maximum value of 5 mV over
the
±
10 V input range. Both the acquisition and settling
times are 850 ns.
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