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參數(shù)資料
| 型號(hào)： | ADG431 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS Precision Quad SPST Switches |
| 中文描述： | LC2MOS精密四路SPST開關(guān) |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 119K |
| 代理商： | ADG431 |
ADG431/ADG432/ADG433
REV. B
–6–
FREQUENCY – Hz
120
100
40
100
10M
1k
O
10k
100k
1M
80
60
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
Figure 7. Off Isolation vs. Frequency
FREQUENCY – Hz
110
100
60100
10M
1k
C
10k
100k
1M
90
80
70
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
Figure 8. Crosstalk vs. Frequency
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors from a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
P
+
P
+
P-CHANNEL
N
+
N
+
N-CHANNEL
P
–
N
–
V
G
V
D
V
S
V
G
V
D
V
S
Figure 9. Trench Isolation
APPLICATION
Figure 10 illustrates a precise, fast sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
OUT
follows the input signal V
IN
. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30
μ
V/
μ
s.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
C
and C
C
. This compensation network also
reduces the hold time glitch while optimizing the acquisition
time. Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the
±
10 V
input range. Both the acquisition and settling times are 850 ns.
+15V
–15V
2200pF
R
C
75
V
C
1000pF
C
H
2200pF
V
OUT
ADG431
ADG432
ADG433
SW1
SW2
S
S
D
D
+15V
+5V
–15V
AD845
+15V
–15V
V
IN
AD711
Figure 10. Fast, Accurate Sample-and-Hold
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADG431ABR | LC2MOS Precision Quad SPST Switches |
| ADG431BN | LC2MOS Precision Quad SPST Switches |
| ADG431BR | LC2MOS Precision Quad SPST Switches |
| ADG431TQ | LC2MOS Precision Quad SPST Switches |
| ADG432ABR | LC2MOS Precision Quad SPST Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADG431ABR | 制造商:Analog Devices 功能描述:IC SWITCH SPST QUAD CMOS |
| ADG431ABR-REEL | 制造商:Analog Devices 功能描述:Analog Switch Quad SPST 16-Pin SOIC N T/R |
| ADG431ABR-REEL7 | 功能描述:IC SWITCH QUAD SPST 16SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:LC²MOS 標(biāo)準(zhǔn)包裝:48 系列:- 功能:開關(guān) 電路:4 x SPST - NO 導(dǎo)通狀態(tài)電阻:100 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| ADG431ABRZ | 制造商:Analog Devices 功能描述:Analog Switch Quad SPST 16-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:TRENCH ISOLATED QUAD SPST SWITCH I.C. - Bulk |
| ADG431ABRZ-REEL7 | 制造商:Analog Devices 功能描述:Analog Switch Quad SPST 16-Pin SOIC N T/R |
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