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參數(shù)資料
| 型號： | ADG428BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | LC2MOS Latchable 4-/8-Channel High Performance Analog Multiplexers |
| 中文描述： | 8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO18 |
| 封裝： | SOIC-18 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 157K |
| 代理商： | ADG428BR |
REV. C
ADG428/ADG429
–5–
ADG428 Truth Table
A2
A1
A0
EN
WR
RS
ON SWITCH
Latching
X
X
X
X
g
1
Maintains Previous
Switch Condition
Reset
X
X
X
X
X
0
NONE
(Latches Cleared)
Transparent Operation
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
ADG429 Truth Table
A1
A0
EN
WR
RS
ON SWITCH PAIR
Latching
X
X
X
g
1
Maintains Previous
Switch Condition
Reset
X
X
X
X
0
NONE
(Latches Cleared)
Transparent Operation
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
NONE
1
2
3
4
TERMINOLOGY
V
DD
V
SS
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
Ground (0 V) reference.
Ohmic resistance between D and S.
Difference between the R
ON
of any two
channels.
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
Channel leakage current when the switch is
on.
Analog voltage on terminals D, S.
Channel input capacitance for “OFF”
condition.
Channel output capacitance for “OFF”
condition.
“ON” switch capacitance.
Digital input capacitance.
Delay time between the 50% and 90% points
of the digital input and switch “ON”
condition.
Delay time between the 50% and 90% points
of the digital input and switch “OFF”
condition.
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
Maximum input voltage for Logic “0.”
Minimum input voltage for Logic “1.”
Input current of the digital input.
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
A measure of unwanted signal coupling
through an “OFF” channel.
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
Positive supply current.
Negative supply current.
GND
R
ON
R
ON
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
D
(V
S
)
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
(EN)
t
OFF
(EN)
t
TRANSITlON
t
OPEN
V
INL
V
INH
I
INL
(I
INH
)
Crosstalk
Off Isolation
Charge
Injection
I
DD
I
SS
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