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| 型號： | ADG3300BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XLATOR 8CH 1.2/5.5V 20-TSSOP |
| 標準包裝： | 1 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 8 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據(jù)速率： | 50Mbps |
| 通道數(shù)： | 8 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 802 (CN2011-ZH PDF) |
| 其它名稱： | ADG3300BRUZ-REEL7DKR |
ADG3300
Rev. 0 | Page 14 of 20
TERMINOLOGY
Table 4.
Symbol
Description
VIHA
Logic input high voltage at Pins A1 to A8.
VILA
Logic input low voltage at Pins A1 to A8.
VOHA
Logic output high voltage at Pins A1 to A8.
VOLA
Logic output low voltage at Pins A1 to A8.
RA,HiZ
Pull-down resistance measured at Pins A1 to A8 when EN = 0.
VIHY
Logic input high voltage at Pins Y1 to Y8.
VILY
Logic input low voltage at Pins Y1 to Y8.
VOHY
Logic output high voltage at Pins Y1 to Y8.
VOLY
Logic output low voltage at Pins Y1 to Y8.
CY
Capacitance measured at Pins Y1 to Y8 (EN = 0).
ILY, HiZ
Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8).
VIHEN
Logic input high voltage at the EN pin.
VILEN
Logic input low voltage at the EN pin.
CEN
Capacitance measured at EN pin.
ILEN
Enable (EN) pin leakage curent.
tEN
Three-state enable time for Pins Y1 to Y8.
tP, A-Y
Propagation delay when translating logic levels in the A Y direction.
tR, A-Y
Rise time when translating logic levels in the A Y direction.
tF, A-Y
Fall time when translating logic levels in the A Y direction.
DMAX, A-Y
Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions
specified in Table 1.
tSKEW, A-Y
Difference between propagation delays on any two channels when translating logic levels in the A Y direction.
tPPSKEW, A-Y
Difference in propagation delay between any one channel and the same channel on a different part (under the
same driving/loading conditions) when translating logic levels in the A Y direction.
tP, Y-A
Propagation delay when translating logic levels in the Y A direction.
tR, Y-A
Rise time when translating logic levels in the Y A direction.
tF, Y-A
Fall time when translating logic levels in the Y A direction.
DMAX, Y-A
Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions
specified in Table 1.
tSKEW, Y-A
Difference between propagation delays on any two channels when translating logic levels in the Y A direction.
tPPSKEW, Y-A
Difference in propagation delay between any one channel and the same channel on a different part (under the
same driving/loading conditions) when translating in the Y A direction.
VCCA
VCCA supply voltage.
VCCY
VCCY supply voltage.
ICCA
VCCA supply current.
ICCY
VCCY supply current.
IHiZA
VCCA supply current during three-state mode (EN = 0).
IHiZY
VCCY supply current during three-state mode (EN = 0).
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