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參數(shù)資料
| 型號： | ADG3233BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH BYPASS 1.65-3.6V 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 邏輯功能： | 變換器，雙向，單向 |
| 位數(shù)： | 2 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 3.5ns |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uSOIC |
| 包裝： | 帶卷 (TR) |
ADG3233
Data Sheet
Rev. B | Page 4 of 16
Parameter1
Symbol
Test Conditions/Comments
Min
Typ2
Max
Unit
VCC = VCC1 = VCC2 = 2.5 V ± 0.2 V
Propagation Delay, tPD
A1
→ Y1 Normal Mode
tPHL, tPLH
CL = 30 pF, VT = VCC/2
4.5
6.2
ns
A2
→ Y2 Normal Mode
tPHL, tPLH
CL = 30 pF, VT = VCC/2
4.5
6.2
ns
A1
→ Y2 Bypass Mode
tPHL, tPLH
CL = 30 pF, VT = VCC/2
4.5
6.5
ns
ENABLE Time EN
→ Y1
t
EN
CL = 30 pF, VT = VCC/2
5
7.2
ns
DISABLE Time EN
→ Y1
tDIS
CL = 30 pF, VT = VCC/2
3.2
4.7
ns
ENABLE Time EN
→ Y2
t
EN
CL = 30 pF, VT = VCC/2
5
7.7
ns
DISABLE Time EN
→ Y2
tDIS
CL = 30 pF, VT = VCC/2
4.8
7.2
ns
VCC = VCC1 = VCC2 = 1.8 V ± 0.15 V
Propagation Delay, tPD
A1
→ Y1 Normal Mode
tPHL, tPLH
CL = 30 pF, VT = VCC/2
6.7
10
ns
A2
→ Y2 Normal Mode
tPHL, tPLH
CL = 30 pF, VT = VCC/2
6.5
10
ns
A1
→ Y2 Bypass Mode
tPHL, tPLH
CL = 30 pF, VT = VCC/2
6.5
10.25
ns
ENABLE Time EN
→ Y1
t
EN
CL = 30 pF, VT = VCC/2
7
10.5
ns
DISABLE Time EN
→ Y1
tDIS
CL = 30 pF, VT = VCC/2
4.4
6.5
ns
ENABLE Time EN
→ Y2
t
EN
CL = 30 pF, VT = VCC/2
7
12
ns
DISABLE Time EN
→ Y2
tDIS
CL = 30 pF, VT = VCC/2
6.5
10.5
ns
Input Leakage Current
II
0 ≤ VIN ≤ 3.6 V
±1
A
Output Leakage Current
IO
0 ≤ VIN ≤ 3.6 V
±1
A
POWER REQUIREMENTS
Power Supply Voltages
VCC1
1.65
3.6
V
VCC2
1.65
3.6
V
Quiescent Power Supply Current
ICC1
Digital inputs = 0 V or VCC
2
A
ICC2
Digital inputs = 0 V or VCC
2
A
Increase in ICC per Input
ΔICC1
VCC = 3.6 V, one input at 3.0 V; others at
VCC or GND
0.75
A
1
Temperature range is as follows: B Version: 40°C to +85°C.
2
All typical values are at VCC = VCC1 = VCC2, TA = 25°C, unless otherwise stated.
3
VIL and VIH levels are specified with respect to VCC1, VOH, and VOL levels for Y1 are specified with respect to VCC1, and VOH, and VOL levels are specified for Y2 with respect to
VCC2.
4
Guaranteed by design, not subject to production test.
5
See the Test Waveforms section.
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