參數(shù)資料
型號(hào): ADG3233BRM-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/16頁(yè)
文件大小: 0K
描述: IC SW LLT 1.65/3.6V BYPASS 8MSOP
標(biāo)準(zhǔn)包裝: 1
邏輯功能: 變換器,雙向,單向
位數(shù): 2
輸入類型: 邏輯
輸出類型: 邏輯
通道數(shù): 1
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無(wú)/無(wú)
傳輸延遲(最大): 3.5ns
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uSOIC
包裝: 剪切帶 (CT)
產(chǎn)品目錄頁(yè)面: 801 (CN2011-ZH PDF)
其它名稱: ADG3233BRMREEL7CT
Data Sheet
ADG3233
Rev. B | Page 13 of 16
THEORY OF OPERATION
The ADG3233 is a bypass switch designed on a submicron
process that operates from supplies as low as 1.65 V. The device
is guaranteed for operation over the supply range 1.65 V to 3.6 V. It
operates from two supply voltages, allowing bidirectional level
translation, that is, it translates low voltages to higher voltages
and vice versa. The signal path is unidirectional, meaning data
may only flow from A → Y.
A1 AND EN INPUT
The A1 and enable (EN) inputs have VIL/VIH logic levels so that
the part can accept logic levels of VOL/VOH from Device 0 or the
controlling device independent of the value of the supply being
used by the controlling device. These inputs (A1, EN) are
capable of accepting inputs outside the VCC1 supply range. For
example, the VCC1 supply applied to the bypass switch could be
1.8 V while Device 0 could be operating from a 2.5 V or 3.3 V
supply rail, there are no internal diodes to the supply rails, so
the device can handle inputs above the supply but inside the
absolute maximum ratings.
NORMAL OPERATION
Figure 35 shows the bypass switch being used in normal mode.
In this mode, the signal paths are from A1 → Y1 and A2 → Y2.
The device will level translate the signal applied to A1 to a VCC1
logic level (this level translation can be either to a higher or
lower supply) and route the signal to the Y1 output, which
will have standard VOL/VOH levels for VCC1 supplies. The signal
is then passed through Device 1 and back to the A2 input pin
of the bypass switch.
The logic level inputs of A2 are with respect to the VCC1 supply.
The signal will be level translated from VCC1 to VCC2 and routed
to the Y2 output pin of the bypass switch. Y2 output logic levels
are with respect to the VCC2 supply.
VCC2
VCC1
VCC0
SIGNAL INPUT
A1
A2
Y1
Y2
LOGIC 1
SIGNAL OUTPUT
DEVICE 0
DEVICE 1
DEVICE 2
VCC2
VCC1
03297-
035
EN
BYPASS SWITCH
Figure 35. Bypass Switch in Normal Mode
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