參數(shù)資料
型號: ADF7020
廠商: Analog Devices, Inc.
英文描述: High Performance ISM Band FSK/ASK Transceiver IC
中文描述: 高性能ISM頻段FSK信號/賣出收發(fā)芯片
文件頁數(shù): 13/40頁
文件大小: 797K
代理商: ADF7020
Preliminary Technical Data
ADF7020
VCO Bias Current
Rev. PrH | Page 13 of 40
VCO bias current can be adjusted using Bits R1_DB19 to
R1_DB16. To ensure VCO oscillation, the minimum bias
current setting under typical conditions is 2.5 mA.
VCO
LOOP FILTER
MUX
VCO SELECT BIT
TO PA AND
N DIVIDER
VCO BIAS
R1_DB (16:19)
220
μ
F
0
CVCO PIN
÷
2
÷
2
Figure 10. Voltage Controlled Oscillator (VCO)
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
The fractional-N PLL allows the selection of any channel within
868 MHz to 928 MHz (and 433MHz using divide-by-2) to a
resolution of <100 Hz. This also facilitates frequency hopping
systems.
Careful selection of the RF transmit channels must be made to
achieve best spurious performance. The architecture of
fractional-N results in some level of the nearest integer channel
moving through the loop to the RF output. These “beat-note”
spurs are not attenuated by the loop, if the desired RF channel
and the nearest integer channel are separated by a frequency of
less than the LBW.
The occurrence of beat-note spurs is rare, because the integer
frequencies are at multiples of the reference, which is typically
>10 MHz.
Beat-note spurs can be significantly reduced in amplitude by
avoiding very small or very large values in the fractional
register, using the frequency doubler. By having a channel
1 MHz away from an integer frequency, a 100 kHz loop filter
can reduce the level to <45 dBc. When using an external VCO,
the fast lock (bleed) function reduces the spurs to <60 dBc for
the same conditions.
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ADF7020BCP 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance ISM Band FSK/ASK Transceiver IC