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參數(shù)資料
| 型號(hào)： | ADF4360-2 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | 綜合合成器和VCO |
| 文件頁(yè)數(shù)： | 17/20頁(yè) |
| 文件大?。?/td> | 336K |
| 代理商： | ADF4360-2 |
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PRELIMINARY TECHNICAL DATA
ADF4360-2
REV. PrA 07/03
–17–
FIXED FREQUENCY LO:
The following diagram shows the ADF4360-2 used as a fixed
frequency LO at 2.0GHz. The low-pass filter was designed
using ADIsimPLL, for a channel spacing of 8MHz and an
open-loop bandwidth of 45kHz. 8MHz is the maximum PFD
frequency of the ADF4360-2. Since using a larger PFD
frequency allows us to use a smaller N. The In-band phase
noise is reduced to as low as possible, -99dBc/Hz. The 40kHz
bandwidth is chosen to be just greater than the point at which
open-loop phase-noise of the VCO is -99dBc/Hz, thus giving
the best possible Integrated noise. The typical rms phase
noise (100Hz-100kHz) of the LO in this configuration is 0.3
degrees.
The reference frequency is from a 16MHz TCXO from Fox.
Thus an R value of 2 is programmed. Taking account of the
high PFD frequency, and the effect this has on the band
select logic, the band select clock divider is enabled. In this
case a value of 8 is chosen. A very simple pull-up resistor and
DC blocking capacitor complete the RF output stage.
Figure 9. Single Frequency LO.
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| ADF4360-2BCP | Integrated Synthesizer and VCO |
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| ADF4360-7BCP | Integrated Synthesizer and VCO |
| ADF4360-5 | Integrated Synthesizer and VCO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4360-2_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| ADF4360-28CPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADF4360-2BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4360-2BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
| ADF4360-2BCPRL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
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