參數(shù)資料
型號(hào): ADF4360-0BCPZRL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 9/24頁(yè)
文件大?。?/td> 0K
描述: IC SYNTHESIZER VCO 24LFCSP
標(biāo)準(zhǔn)包裝: 1,500
類型: 扇出配送,整數(shù)-N,合成器(RF)
PLL:
輸入: CMOS,TTL
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 2.725GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 帶卷 (TR)
Data Sheet
ADF4360-0
Rev. C | Page 17 of 24
Hardware Power-Up/Power-Down
If the ADF4360-0 is powered down via the hardware (using the
CE pin) and powered up again without any change to the N
counter register during power-down, it locks at the correct fre-
quency because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <5 ms for 10 F capacitance. The smaller
capacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while it is in power-
down because the part may not lock to the correct frequency on
power-up. If it is updated, the correct programming sequence
for it after power-up is to the R counter latch, followed by the
control latch, and finally the N counter latch, with the required
interval between the control latch and N counter latch, as
described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the ADF4360-0 is powered down via the software (using the
control latch) and powered up again without any change to the
N counter latch during power-down, it locks at the correct fre-
quency because it is already in the correct frequency band. The
lock time depends on the value of capacitance on the CN pin,
which is <5 ms for 10 F capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while it is in power-
down because the part may not lock to the correct frequency on
power-up. If it is updated, the correct programming sequence
for it after power-up is to the R counter latch, followed by the
control latch, and finally the N counter latch, with the required
interval between the control latch and N counter latch, as
described in the Initial Power-Up section.
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