參數(shù)資料
型號: ADF4350BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 18/32頁
文件大?。?/td> 0K
描述: IC SYNTH PLL VCO FN/IN 32LFCSP
產(chǎn)品變化通告: ADF4350, ADF4905/6 N-counter Change 05/Mar/2012
設(shè)計資源: Broadband Low EVM Direct Conversion Transmitter (CN0134)
Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144)
Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147)
標(biāo)準(zhǔn)包裝: 1
類型: 扇出配送,分?jǐn)?shù)-N,整數(shù)-N,時鐘/頻率合成器(RF)
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 4.4GHz
除法器/乘法器: 是/是
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
ADF4350
Rev. A | Page 25 of 32
APPLICATIONS INFORMATION
DIRECT CONVERSION MODULATOR
Direct conversion architectures are increasingly being used to
implement base station transmitters. Figure 34 shows how Analog
Devices, Inc., parts can be used to implement such a system.
The circuit block diagram shows the AD9761 TxDAC being
used with the ADL5375. The use of dual integrated DACs, such
as the AD9788 with its specified ±0.02 dB and ±0.001 dB gain
and offset matching characteristics, ensures minimum error
contribution (over temperature) from this portion of the
signal chain.
The local oscillator (LO) is implemented using the ADF4350.
The low-pass filter was designed using ADIsimPLL for a channel
spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.
The LO ports of the ADL5375 can be driven differentially from
the complementary RFOUTA and RFOUTB outputs of the ADF4350.
This gives better performance than a single-ended LO driver
and eliminates the use of a balun to convert from a single-ended
LO input to the more desirable differential LO input for the
ADL5375. At LO frequencies below 3 GHz some harmonic
filtering may be necessary to ensure best single sideband
performance.
The ADL5375 accepts LO drive levels from 6 dBm to +7 dBm.
The optimum LO power can be software programmed on the
ADF4350, which allows levels from 4 dBm to +5 dBm from
each output. For more details on this circuit, consult CN-0134.
The RF output is designed to drive a 50 Ω load, but must be
ac-coupled, as shown in Figure 34. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power from the modulator is approximately 2 dBm.
0
732
5-
0
21
2700pF
1200pF
39nF
680
360
S
P
I-
C
O
M
P
A
T
IB
L
E
S
E
R
IA
L
B
U
S
ADF4350
VVCO
CPGND
AGND
DGND
RFOUTB–
RFOUTB+
CPOUT
1nF
4.7k
RSET
LE
DATA
CLK
REFIN
FREFIN
VTUNE
DVDD AVDD CE
MUXOUT
10
28
16
29
1
2
3
22
8
31
9
11 18 21
27
VDD
LOCK
DETECT
51
AGNDVCO
VCOM
14
15
19
23
24
25
30
LD
17
20
7
PDBRF
26
SDGND
TEMP
VREF
6
32
SDVDD
VP
5
SW
10pF
0.1F 10pF
0.1F
4
AD9761
TxDAC
REFIO
FSADJ
MODULATED
DIGITAL
DATA
QOUTB
IOUTA
IOUTB
QOUTA
2k
LOW-PASS
FILTER
LOW-PASS
FILTER
IBBP
IBBN
QBBP
QBBN
LOIP
LOIN
51
ADL5375
RFO
QUADRATURE
PHASE
SPLITTER
DSOP
RFOUTA–
RFOUTA+
13
12
VVCO
3.9nH
1nF
LPF
Figure 34. Direct Conversion Modulator
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