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參數(shù)資料
| 型號： | ADF4252BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 時(shí)鐘/頻率合成器（RF/IF），分?jǐn)?shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4252EBZ2-ND - BOARD EVAL ADF4252 NO VCO/FILTER |
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REV. B
ADF4252
–11–
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 3. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
REFIN NC
NC
NO
SW3
SW2
SW1
100k
BUFFER
TO R
COUNTER
NC = NORMALLY CLOSED
NO = NORMALLY OPEN
REFOUT
XOEB
Figure 3. Reference Input Stage
RF and IF Input Stage
The RF input stage is shown in Figure 4. The IF input stage is
the same. It is followed by a two-stage limiting amplifier to
generate the CML clock levels needed for the N counter.
2k
1.6V
BIAS
GENERATOR
RFINA
RFINB
VDD1
AGND
Figure 4. RF Input Stage
RF INT Divider
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 255 are allowed.
INT, FRAC, MOD, and R Relationship
The INT, FRAC, and MOD values, in conjunction with the
RF R counter, make it possible to generate output frequencies
that are spaced by fractions of the RF phase frequency detector
(PFD). The equation for the RF VCO frequency (RFOUT) is
RF
F
INT
FRAC
MOD
OUT
PFD
=×
+
(1)
where RFOUT is the output frequency of external voltage controlled
oscillator (VCO).
FREF
D
R
PFD
IN
=×
+
()
1
(2)
REFIN = the reference input frequency, D = RF REFIN doubler
bit, R = the preset divide ratio of the binary 4-bit program-
mable reference counter (1 to 15), INT = the preset divide ratio of
the binary 8-bit counter (31 to 255), MOD = the preset modulus
ratio of binary 12-bit programmable FRAC counter (2 to 4095),
and FRAC = the preset fractional ratio of the binary 12-bit
programmable FRAC counter (0 to MOD).
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
RF N DIVIDER
THIRD ORDER
FRACTIONAL
INTERPOLATOR
MOD
REG
INT
REG
FRAC
VALUE
N-COUNTER
Figure 5. N Counter
RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the RF PFD. Division ratios from 1 to 15 are allowed.
IF R Counter
The 15-bit IF R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the IF PFD. Division ratios from 1 to 32767 are allowed.
IF Prescaler (P/P + 1)
The dual modulus IF prescaler (P/P + 1), along with the IF A
and B counters, enables the large division ratio, N, to be realized
(N = PB + A). Operating at CML levels, it takes the clock from
the IF input stage and divides it down to a manageable frequency
for the CMOS IF A and B counters.
IF A and B Counters
The IF A and B CMOS counters combine with the dual modulus
IF prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are guaranteed to work when the
prescaler output is 150 MHz or less.
Pulse Swallow Function
The IF A and B counters, in conjunction with the dual modulus
IF prescaler, make it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.
See Device Programming after Initial Power-Up section for
examples. The equation for the IF VCO (IFOUT) frequency is
IF
P
B
A
F
OUT
PFD
=×
()+
[]×
(3)
where IFOUT = the output frequency of the external voltage controlled
oscillator (VCO), P = the preset modulus of IF dual modulus
prescaler, B = the preset divide ratio of the binary 12-bit counter
(3 to 4095), and A = the preset divide ratio of the binary 6-bit
swallow counter (0 to 63). FPFD is obtained using Equation 2.
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