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參數(shù)資料
| 型號： | ADF4212LBRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADF4212L
Rev. E | Page 13 of 28
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 26. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
REFIN NC
NC
NO
SW3
SW2
SW1
100k
BUFFER
TO R COUNTER
NC = NO CONNECT
02774-
026
Figure 26. Reference Input Stage
RF/IF INPUT STAGE
The RF/IF input stage is shown in Figure 27. It is followed by a
two-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
2k
1.6V
BIAS
GENERATOR
RFIN
AVDD
AGND
100pF
02774-
027
Figure 27. RF/IF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
PB + A). The dual modulus prescaler, operating at CML levels,
takes the clock from the RF/IF input stage and divides it down
to a manageable frequency for the A and B CMOS counters in the
RF and IF sections. The prescaler in both sections is programma-
ble. It can be set in software to 8/9, 16/17, 32/33, or 64/65 (see
Table 9 and Table 10). It is based on a synchronous 4/5 core.
RF/IF A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 188 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
PULSE SWALLOW FUNCTION
The A and B CMOS counters, in conjunction with the dual
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is as follows:
fVCO = [(P × B) + A] × fREFIN/R
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of the dual modulus prescaler (8/9,
16/17, and so on).
B is the preset divide ratio of the binary 12-bit counter (3 to 4095).
A is the preset divide ratio of the binary 6-bit swallow counter
(0 to 63).
fREFIN is the external reference oscillator frequency.
R is the preset divide ratio of the binary 15-bit programmable
reference counter (1 to 32,767).
TO PFD
N = BP + A
LOAD
MODULUS
CONTROL
FROM RF
INPUT STAGE
12-BIT B
COUNTER
6-BIT A
COUNTER
PRESCALER
P/P + 1
02774-
028
Figure 28. RF/IF A and B Counters
RF/IF R COUNTER
The 15-bit RF/IF R counter allows the input reference frequency to
be divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
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| ADF4213BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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