參數(shù)資料
型號: ADF4212LBRU
廠商: ANALOG DEVICES INC
元件分類: XO, clock
英文描述: Dual Low Power PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2400 MHz, PDSO20
封裝: MO-153AC, TSSOP-20
文件頁數(shù): 5/20頁
文件大小: 245K
代理商: ADF4212LBRU
REV. 0
ADF4212L
–5–
PIN FUNCTION DESCRIPTION
Mnemonic
Description
RF Charge Pump Output. When enabled, this provides
±
I
CP
to the external RF loop filter, which in turn drives the
external RF VCO.
Digital Ground Pin for the RF Digital Circuitry
Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry
Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resistance of 100 k
.
See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Digital Ground Pin for the IF Digital, Interface, and Control Circuitry
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF, or the scaled Reference Frequency
to be accessed externally.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The
nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
CP
RF
DGND
RF
RF
IN
AGND
RF
FL
O
REF
IN
DGND
IF
MUXOUT
CLK
DATA
LE
R
SET
I
R
CP MAX
SET
=
13 5
so, with
R
SET
= 2.7 k
,
I
CP MAX
= 5 mA for both the RF and IF Charge Pumps.
Ground Pin for the IF Analog Circuitry
Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.
Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
2. In systems where V
DD
2 is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.
Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be placed
as close as possible to this pin. V
DD
2 should have a value of between 2.6 V and 3.3 V. V
DD
2 must have the same
potential as V
DD
1.
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible to
this pin. V
DD
1 should have a value of between 2.6 V and 3.3 V. V
DD
1 must have the same potential as V
DD
2.
Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
1. In systems where V
DD
1 is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.
AGND
IF
IF
IN
CP
IF
V
P
2
V
DD
2
V
DD
1
V
P
1
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