參數(shù)資料
型號： ADF4193BCPZ-RL
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： Low Phase Noise, Fast Settling PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
文件頁數(shù)： 9/28頁
文件大?。?/td> 437K
代理商： ADF4193BCPZ-RL
ADF4193
Rev. B | Page 9 of 28
0
TIME (
μ
s)
(
–1
0
1
2
3
4
5
9
8
7
6
5
4
3
2
1
0
V
TUNE
CP
OUT+
CP
OUT–
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 4
μ
s.
Figure 10. V
TUNE
Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz with Sirenza 1843T VCO
0
TIME (
μ
s)
P
–5
0
5
10
15
20
25
30
35
40
–50
50
40
30
20
10
0
–10
–20
–30
–40
45
+25
°
C
+85
°
C
–40
°
C
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
PEAK PHASE ERROR < 5
°
@ 17.8
μ
s
Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to
1893 MHz (V
TUNE
1.8 V to 3.7 V with Sirenza 1843T VCO)
0
CP
OUT
+ / CP
OUT
– VOLTAGE (V)
I
C
M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–8
–6
–4
–2
0
2
4
6
8
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
5.0
ICP
OUT
+ P, ICP
OUT
– P
CHARGE PUMP MISMATCH (%)
NORMAL OPERATING RANGE
ICP
OUT
+ N, ICP
OUT
– N
I
UP
= | ICP
+ P | + | ICP
– N |
I
DOWN
= | ICP
OUT
– P | + | ICP
OUT
+ N |
Figure 12. Differential Charge Pump Output Compliance Range and
Charge Pump Mismatch with V
P
1 = V
P
2 = 5 V
0
TIME (
μ
s)
(
–1
0
1
2
3
4
5
9
8
7
6
5
4
3
2
1
0
V
TUNE
CP
OUT–
CP
OUT+
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
FREQUENCY LOCK IN WIDE BW MODE @ 5
μ
s.
Figure 13. V
TUNE
Settling Transient for a 75 MHz Jump Down from 1893 MHz to
1818 MHz, the Bottom of the Allowed Tuning Range with the Sirenza 1843T VCO
0
TIME (
μ
s)
P
–5
0
5
10
15
20
25
30
35
40
–50
50
40
30
20
10
0
–10
–20
–30
–40
45
+25
°
C
+85
°
C
–40
°
C
DCS1800 Tx SETUP, 60kHz LOOP BW.
MEASURED ON EVAL-ADF4193-EB1
EVALUATION BOARD WITH AD8302
PHASE DETECTOR.
TIMERS: ICP = 28, SW1/SW2, SW3 = 35.
PEAK PHASE ERROR < 5
°
@ 19.2
μ
s
Figure 14. Phase Settling Transient for a 75 MHz Jump from 1893 MHz to
1818 MHz (V
TUNE
= 3.7 V to 1.8 V with Sirenza 1843T VCO)
0
FREQUENCY (MHz)
(
1780
1800
1820
1840
1860
1880
1900
1920
1940
0
2
1
3
4
5
V
P
1 = V
2 = 5V
V
P
3 = 5.5V
V
CMR
= 3.3V
CP
OUT–
(= AIN–)
A
OUT
(= V
TUNE
)
CP
OUT+
(= AIN+)
Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential
Amplifier Power Supply Voltage
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相關代理商/技術參數(shù)
參數(shù)描述
ADF4193BCPZ-RL7 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
ADF4193SP1BCPZ 制造商:Analog Devices 功能描述:
ADF4193SP1BCPZ-RL7 制造商:Analog Devices 功能描述:
ADF4193SP2BCPZ-RL7 制造商:Analog Devices 功能描述:
ADF4193WCCPZ-RL7 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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