參數(shù)資料
型號(hào)： ADF4158CCPZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 0K
描述： IC FRACTION N FREQ SYNT 24LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 分?jǐn)?shù) N 合成器（RF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 6.1GHz
除法器/乘法器： 是/是
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： *
包裝： 托盤(pán)
Data Sheet
ADF4158
Rev. G | Page 25 of 36
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
After powering up the part, administer the following
programming sequence:
1. Delay register (R7)
2. Step register (R6)—load the step register (R6) twice, first
with STEP SEL = 0 and then with STEP SEL = 1
3. Deviation register (R5)—load the deviation register (R5)
twice, first with DEV SEL = 0 and then with DEV SEL = 1
4. Test register (R4)
5. Function register (R3)
6. R-divider register (R2)
7. LSB FRAC register (R1)
8. FRAC/INT register (R0)
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RFOUT = [N + (FRAC/225)] × [fPFD]
(4)
where:
RFOUT is the RF frequency output.
N is the integer division factor.
FRAC is the fractionality.
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(5)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide-by-2 bit (0 or 1).
For example, in a system where a 5.8002 GHz RF frequency
output (RFOUT) is required and a 10 MHz reference frequency
input (REFIN) is available, the frequency resolution is
fRES = REFIN/225
(6)
fRES = 10 MHz/225
= 0.298 Hz
From Equation 5,
fPFD = [10 MHz × (1 + 0)/1] = 10 MHz
5.8002 GHz = 10 MHz × (N + FRAC/225)
Calculating N and FRAC values,
N = int(RFOUT/fPFD) = 580
FRAC = FMSB × 213 + FLSB
FMSB = int(((RFOUT/fPFD) N) × 212) = 81
FLSB = int(((((RFOUT/fPFD) N) × 212) FMSB) × 213) = 7537
where:
FMSB is the 12-bit MSB FRAC value in Register R0.
FLSB is the 13-bit LSB FRAC value in Register R1.
int() makes an integer of the argument in parentheses.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the noise
performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB.
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the Σ-Δ circuit of the
N-divider.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast-locking applications, a wide loop filter bandwidth is
required for fast frequency acquisition, resulting in increased
integrated phase noise and reduced spur attenuation. Using cycle
slip reduction, the loop bandwidth can be kept narrow to
reduce integrated phase noise and attenuate spurs while still
realizing fast lock times.
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared with the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the PLL
to correct, and the charge pump temporarily pumps in the wrong
direction, slowing down the lock time dramatically. The ADF4158
contains a cycle slip reduction circuit to extend the linear range
of the PFD, allowing faster lock times without loop filter changes.
When the ADF4158 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. This outputs a
constant current to the loop filter or removes a constant current
from the loop filter (depending on whether the VCO tuning
voltage needs to increase or decrease to acquire the new
frequency). The effect is that the linear range of the PFD is
increased. Stability is maintained because the current is
constant and is not a pulsed current.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4158 turns on another charge pump cell. This
continues until the ADF4158 detects that the VCO frequency
has gone past the desired frequency. It then begins to turn off
the extra charge pump cells one by one until they are all turned
off and the frequency is settled.
Up to seven extra charge pump cells can be turned on. In most
applications, it is enough to eliminate cycle slips altogether,
giving much faster lock times.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF4158CCPZ 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 6.1GHZ, LFCS
ADF4158CCPZ-RL7 功能描述:IC FRACTION N FREQ SYNT 24LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱(chēng):SY58052UMGTRSY58052UMGTR-ND
ADF4158WCCPZ 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤(pán) 零件狀態(tài):在售 類(lèi)型:分?jǐn)?shù) N 合成器（RF） PLL:是 輸入:CMOS，TTL 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大值:6.1GHz 分頻器/倍頻器:是/是 電壓 - 電源:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-WFQFN 裸露焊盤(pán) 供應(yīng)商器件封裝:24-LFCSP-WQ（4x4） 標(biāo)準(zhǔn)包裝:1
ADF4158WCCPZ-RL7 功能描述:IC FRAC-N FREQ SYNTH 24LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱(chēng):SY58052UMGTRSY58052UMGTR-ND
ADF4159 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer
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