- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9098 > ADF4157BRUZ-RL (Analog Devices Inc)IC PLL FREQ SYNTH 6GHZ 16TSSOP PDF資料下載
參數(shù)資料
| 型號： | ADF4157BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTH 6GHZ 16TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 分數(shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4157EB1Z-ND - BOARD EVALUATION FOR ADF4157 |
ADF4157
Data Sheet
Rev. D | Page 10 of 24
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and the N counter
and produces an output proportional to the phase and fre-
quency difference between them. Figure 14 is a simplified
schematic of the phase frequency detector. The PFD includes
a fixed delay element that sets the width of the antibacklash
pulse, which is typically 3 ns. This pulse ensures that there is no
dead zone in the PFD transfer function and gives a consistent
reference spur level.
U3
CLR2
Q2
D2
U2
DOWN
UP
HI
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
05874-
008
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4157 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by M4, M3, M2, and M1 (see Figure 17). Figure 15
shows the MUXOUT section in block diagram form.
05874-
009
ANALOG LOCK DETECT
MUXOUT
DVDD
THREE-STATE OUTPUT
N DIVIDER OUTPUT
DVDD
DGND
R DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R DIVIDER/2
N DIVIDER/2
CONTROL
MUX
FASTLOCK SWITCH
Figure 15. MUXOUT Schematic
INPUT SHIFT REGISTER
The ADF4157 digital section includes a 5-bit RF R counter, a
12-bit RF N counter, and a 25-bit FRAC counter. Data is clocked
into the 32-bit input shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
input shift register to one of five latches on the rising edge of
LE. The destination latch is determined by the state of the three
control bits (C3, C2, and C1) in the input shift register. These
are the three LSBs, DB2, DB1, and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 16
shows a summary of how the latches are programmed.
PROGRAM MODES
the program modes in the ADF4157.
Several settings in the ADF4157 are double-buffered. These
include the LSB FRAC value, R counter value, reference doubler,
and current setting. This means that two events have to occur
before the part uses a new value of any of the double-buffered
settings. First, the new value is latched into the device by writing to
the appropriate register. Second, a new write must be performed
on Register 0, R0.
For example, updating the fractional value can involve a write
to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should
be written to first, followed by the write to R0. The frequency
change begins after the write to R0. Double buffering ensures
that the bits written to in R1 do not take effect until after the
write to R0.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
Register
0
Register 0 (R0)
0
1
Register 1 (R1)
0
1
0
Register 2 (R2)
0
1
Register 3 (R3)
1
0
Register 4 (R4)
相關PDF資料 |
PDF描述 |
|---|---|
| ADF4157BCPZ-RL | IC PLL FREQ SYNTH 6GHZ 20LFCSP |
| X9400WV24I-2.7T1 | IC XDCP QUAD 64-TAP 10K 24-TSSOP |
| ISPPAC-CLK5312S-01T48C | IC BUFFER FANOUT ISP UNIV 48TQFP |
| X9400WV24-2.7T1 | IC XDCP QUAD 64-TAP 10K 24-TSSOP |
| VI-B7H-MY-F3 | CONVERTER MOD DC/DC 52V 50W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4157BRUZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4157BRUZ-RL7 | 功能描述:IC PLL FREQ SYNTH 6GHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4157BRUZ-RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4158 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer |
| ADF4158CCPZ | 功能描述:IC FRACTION N FREQ SYNT 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復。