- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375254 > ADF4157BRUZ-RL1 (Analog Devices, Inc.) High Resolution 6 GHz Fractional-N Frequency Synthesizer PDF資料下載
參數(shù)資料
| 型號： | ADF4157BRUZ-RL1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| 中文描述： | 高分辨率6 GHz的分?jǐn)?shù)N頻率合成器 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 320K |
| 代理商： | ADF4157BRUZ-RL1 |
ADF4157
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
After powering up the part, this programming sequence must
be followed:
1.
Test Register (R4)
2.
Function Register (R3)
3.
R Divider Register (R2)
4.
LSB FRAC Register (R1)
5.
FRAC/INT Register (R0)
Rev. 0 | Page 17 of 20
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RF
OUT
= [
N
+ (
FRAC/
2
25
)] × [
f
PFD
]
where:
RF
OUT
is the RF frequency output.
N
is the integer division factor.
FRAC
is the fractionality.
f
PFD
=
REF
IN
× [(1 +
D
)/(
R × (
1
+ T))]
where:
REF
IN
is the reference frequency input.
D
is the RF REF
IN
doubler bit.
R
is the RF reference division factor.
T
is the reference divide-by-2 bit (0 or 1).
For example, in a system where a 5.8002 GHz RF frequency
output (RF
OUT
) is required and a 10 MHz reference frequency
input (REF
IN
) is available, the frequency resolution is
f
RES
=
REF
IN
/2
25
f
RES
= 10 MHz/2
25
= 0.298 Hz
From Equation 4,
f
PFD
= [10 MHz × (1 + 0)/1] = 10 MHz
5.8002 GHz = 10 MHz × (
N
+
FRAC/
2
25
)
Calculating N and FRAC values,
N
=
int
(
RF
OUT
/
f
PFD
) = 580
FRAC
=
F
MSB
× 2
13
+
F
LSB
F
MSB
=
int
(((
RF
OUT
/
f
PFD
) N) × 2
12
) = 81
F
LSB
=
int
(((((
RF
OUT
/
f
PFD
) N) × 2
12
)
F
MSB
) × 2
13
) = 7537
where:
F
MSB
is the 12-bit MSB FRAC value in Register R0.
F
LSB
is the 13-bit LSB FRAC value in Register R1.
int
() makes an integer of the argument in brackets.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the noise
performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
(3)
(4)
note that the PFD cannot be operated above 32 MHz due to
a limitation in the speed of the Σ-Δ circuit of the N divider.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast-locking applications, a wide loop filter bandwidth is
required for fast frequency acquisition, resulting in increased
integrated phase noise and reduced spur attenuation. Using
cycle slip reduction, the loop bandwidth can be kept narrow to
reduce integrated phase noise and attenuate spurs while still
realizing fast lock times.
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared to the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the PLL
to correct, and the charge pump temporarily pumps in the wrong
direction, slowing down the lock time dramatically. The ADF4157
contains a cycle slip reduction circuit to extend the linear range
of the PFD, allowing faster lock times without loop filter changes.
When the ADF4157 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. This outputs a constant
current to the loop filter or removes a constant current from the
loop filter (depending on whether the VCO tuning voltage needs
to increase or decrease to acquire the new frequency). The effect is
that the linear range of the PFD is increased. Stability is main-
tained because the current is constant and is not a pulsed current.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4157 turns on another charge pump cell.
This continues until the ADF4157 detects that the VCO
frequency has gone past the desired frequency. It then begins to
turn off the extra charge pump cells one by one until they are all
turned off and the frequency is settled.
Up to seven extra charge pump cells can be turned on. In most
applications, it is enough to eliminate cycle slips altogether,
giving much faster lock times.
Setting Bit DB28 in the R Divider register (R2) to 1 enables
cycle slip reduction. Note that a 45% to 55% duty cycle is
needed on the signal at the PFD in order for CSR to operate
correctly. The reference divide-by-2 flip-flop can help to
provide a 50% duty cycle at the PFD. For example, if a 100 MHz
reference frequency is available, and the user wants to run the
PFD at 10 MHz, setting the R divide factor to 10 results in a 10
MHz PFD signal that is not 50% duty cycle. By setting the R
divide factor to 5 and enabling the reference divide-by-2 bit, a
50% duty cycle 10 MHz signal can be achieved.
Note that the cycle slip reduction feature can only be operated
when the phase detector polarity setting is positive (DB6 in
Register R3). It cannot be used if the phase detector polarity is
set to negative.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4157BRUZ-RL71 | High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4207 | Dual PLL Frequency Synthesizer(雙鎖相環(huán)頻率合成器) |
| ADF4208 | Dual PLL Frequency Synthesizer(雙鎖相環(huán)頻率合成器) |
| ADF4212LBCP | Dual Low Power PLL Frequency Synthesizer |
| ADF4212LBRU | Dual Low Power PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4157BRUZ-RL7 | 功能描述:IC PLL FREQ SYNTH 6GHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4157BRUZ-RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4158 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer |
| ADF4158CCPZ | 功能描述:IC FRACTION N FREQ SYNT 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4158CCPZ | 制造商:Analog Devices 功能描述:PLL, FREQUENCY SYNTHESIZER, 6.1GHZ, LFCS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。