參數(shù)資料
型號(hào): ADF4157BCPZ1
廠商: Analog Devices, Inc.
英文描述: High Resolution 6 GHz Fractional-N Frequency Synthesizer
中文描述: 高分辨率6 GHz的分?jǐn)?shù)N頻率合成器
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 320K
代理商: ADF4157BCPZ1
ADF4157
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 20
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AV
DD
RF
IN
A
RF
IN
B
R
SET
DV
DD
MUXOUT
LE
CE
REF
IN
DGND
CLK
DATA
V
P
ADF4157
TOP VIEW
(Not to Scale)
0
PIN 1
INDICATOR
1
2
3
4
5
CPGND
AGND
AGND
RF
IN
B
RF
IN
A
13 DATA
12 CLK
11 CE
14 LE
15 MUXOUT
6
A
D
7
A
D
8
R
I
1
D
9
D
1
P
1
S
2
1
D
1
D
TOP VIEW
(Not to Scale)
ADF4157
0
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
LFCSP
1
19
Mnemonic
R
SET
Description
Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between I
CP
and R
SET
is
5
25
=
SET
CPMAX
R
I
where:
R
SET
= 5.1 kΩ.
I
CPMAX
= 5 mA.
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter which, in turn, drives
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
DD
has a value of 3 V ± 10%. AV
DD
must have the same voltage as
DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-
coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is
a high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of
the five latches, the latch being selected using the control bits.
This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
DD
has a value of 3 V ± 10%. DV
DD
must have the same voltage as
AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
2
20
CP
3
4
5
1
2, 3
4
CPGND
AGND
RF
IN
B
6
7
5
6, 7
RF
IN
A
AV
DD
8
8
REF
IN
9
10
9, 10
11
DGND
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DV
DD
16
18
V
P
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PDF描述
ADF4157BCPZ-RL1 High Resolution 6 GHz Fractional-N Frequency Synthesizer
ADF4157BCPZ-RL71 High Resolution 6 GHz Fractional-N Frequency Synthesizer
ADF4157BRUZ1 High Resolution 6 GHz Fractional-N Frequency Synthesizer
ADF4157BRUZ-RL1 High Resolution 6 GHz Fractional-N Frequency Synthesizer
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ADF4157BCPZ-RL1 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer
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ADF4157BCPZ-RL71 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer
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