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參數(shù)資料
| 型號： | ADF4157 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| 中文描述： | 高分辨率6 GHz的分數(shù)N頻率合成器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 320K |
| 代理商： | ADF4157 |
ADF4157
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
Rev. 0 | Page 8 of 20
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (
RF
OUT
) equation is
RF
OUT
=
f
PFD
× (
INT
+ (
FRAC/
2
25
))
where:
RF
OUT
is the output frequency of the external voltage controlled
oscillator (VCO).
INT
is the preset divide ratio of the binary 12-bit counter (23 to
4095).
FRAC
is the numerator of the fractional division (0 to 2
25
1).
f
PFD
=
REF
IN
× [(1 +
D
)/(
R × (
1
+T))]
where:
REF
IN
is the reference input frequency.
D
is the REF
IN
doubler bit.
R
is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
T
is the REF
IN
divide-by-2 bit (0 or 1).
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
RF
(1)
BUFFER
TO R COUNTER
REF
IN
100k
NC
SW2
SW3
NC
NC
SW1
POWER-DOWN
CONTROL
0
Figure 11. Reference Input Stage
(2)
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by
a 2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AV
DD
2k
2k
RF
IN
B
RF
IN
A
0
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
0
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4157 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
f
RES
=
f
PFD
/2
25
where
f
PFD
is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
Figure 13. RF N Divider
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4157BCPZ | 功能描述:IC PLL FREQ SYNTH 6GHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4157BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
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| ADF4157BCPZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4157BCPZ-RL7 | 功能描述:IC PLL FREQ SYNTH 6GHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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