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參數資料
| 型號： | ADF4156BRUZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | 6 GHz Fractional-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 6200 MHz, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-153AB, TSSOP-16 |
| 文件頁數： | 9/24頁 |
| 文件大?。?/td> | 314K |
| 代理商： | ADF4156BRUZ-RL |
ADF4156
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse, which is
typically 3 ns. This pulse ensures that there is no dead zone in the
PFD transfer function, and gives a consistent reference spur level.
Rev. 0 | Page 9 of 24
U3
CLR2
D2
U2
Q2
DOWN
UP
HI
HI
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
0
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4156 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M4, M3, M2, and M1 (for details,
see Figure 16). Figure 15 shows the MUXOUT section in block
diagram form.
ANALOG LOCK DETECT
MUXOUT
DV
DD
THREE-STATE OUTPUT
N DIVIDER OUTPUT
DV
DD
DGND
DGND
R DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R DIVIDER/2
N DIVIDER/2
CONTROL
0
MUX
Figure 15. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4156 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of five latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2 and C1) in the shift
register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in
Figure 2. The truth table for these bits is shown in Table 6.
Figure 16 shows a summary of how the latches are programmed.
PROGRAM MODES
Table 6 and Figure 16 through Figure 20 show how to set up the
program modes in the ADF4156.
A number of settings in the ADF4156 are double buffered.
These include the modulus value, phase value, R counter value,
reference doubler, reference divide-by-2, and current setting.
This means that two events have to occur before the part uses a
new value of any of the double buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R0.
For example, any time that the modulus value has been
updated, Register R0 must be written to after this, to ensure that
the modulus value is loaded correctly.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Register
Register R0
Register R1
Register R2
Register R3
Register R4
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相關代理商/技術參數 |
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| ADF4156BRUZ-RL7 | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156SP1BRUZ | 制造商:Analog Devices 功能描述: |
| ADF4157 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
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| ADF4157BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
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