參數(shù)資料
型號(hào)： ADF4156BCPZ-RL
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： 6 GHz Fractional-N Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 6200 MHz, QCC20
封裝： 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-1, LFCSP-20
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 314K
代理商： ADF4156BCPZ-RL
ADF4156
The evaluation software has a sweep function to sweep the
PHASE word so that the user can observe the spur levels on a
spectrum analyzer.
Rev. 0 | Page 19 of 24
If a look-up table is not used, keep the PHASE word at a
constant value to ensure consistent spur levels on any particular
frequency.
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of MOD
phase offsets with respect to the input reference; where MOD is
the fractional modulus. The PHASE resync feature in the
ADF4156 is used to produce a consistent output phase offset
with respect to the input reference. This is necessary in
applications where the output phase and frequency are
important, such as digital beam forming. See the section,
PHASE Programmability, for how to program a specific RF
output phase when using PHASE resync.
PHASE resync is enabled by setting Bit DB20 and Bit DB19 in
Register R4 to [1, 0]. When PHASE resync is enabled, an
internal timer generates sync signals at intervals of T
SYNC
given
by the following formula:
T
SYNC
=
CLK_DIV_VALUE
×
MOD
×
T
PFD
where:
T
PFD
is the PFD reference period.
CLK_DIV_VALUE
is the decimal value programmed in
Bit DB[18:7] of Register R4, and can be any integer in the range
of 1 to 4095.
MOD
is the modulus value programmed in Bit DB[14:3] of
Register R1.
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The T
SYNC
time should be programmed
to a value that is as least as long as the worst-case lock time.
Doing so guarantees that the PHASE resync occurs after the last
cycle slip in the PLL settling transient.
In the example shown in Figure 22, the PFD reference is
25 MHz and MOD = 125 for a 200 kHz channel spacing. T
SYNC
is set to 400 μs by programming CLK_DIV_VALUE = 80.
LE
PHASE
FREQUENCY
SYNC
(Internal)
–100
0
100
200
1000
300
400
TIME (μs)
500
600
700
800
900
0
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
T
SYNC
LAST CYCLE SLIP
PLL SETTLES TO
INCORRECT PHASE
Figure 22. PHASE Resync Example
PHASE Programmability
In order to program a specific RF output phase, the PHASE
word in Register R1 should be changed. As this word is swept
from 0 to MOD, the RF output phase sweeps over a 360
o
/MOD
range in steps of 360
o
/MOD.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum,
however, RF frequencies lower than this can be used providing
the minimum slew rate specification of 400 V/μs is met. An
appropriate LVDS driver can be used to square up the RF signal
before it is fed back to the ADF4156 RF input. The FIN1001
from Fairchild Semiconductor is one such LVDS driver.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help the user
to implement PLL design. Visit
www.analog.com/pll
for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed. In designing the loop filter, the ratio
of PFD frequency to loop bandwidth should be kept >200:1.
This is to attenuate the SDM noise.
相關(guān)PDF資料
PDF描述
ADF4156BCPZ-RL7 6 GHz Fractional-N Frequency Synthesizer
ADF4156BRUZ 6 GHz Fractional-N Frequency Synthesizer
ADF4156BRUZ-RL 6 GHz Fractional-N Frequency Synthesizer
ADF4156BRUZ-RL7 6 GHz Fractional-N Frequency Synthesizer
ADF4157 High Resolution 6 GHz Fractional-N Frequency Synthesizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF4156BCPZ-RL7 功能描述:IC PLL FRAC-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
ADF4156BCPZ-U1 制造商:Analog Devices 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Trays
ADF4156BRUZ 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
ADF4156BRUZ-RL 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
ADF4156BRUZ-RL7 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*