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參數(shù)資料
| 型號： | ADF4156BCPZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | 6 GHz Fractional-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 6200 MHz, QCC20 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-1, LFCSP-20 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 314K |
| 代理商： | ADF4156BCPZ-RL7 |
ADF4156
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RF
OUT
= [
INT
+ (
FRAC
/
MOD
)] × [
F
PFD
]
Rev. 0 | Page 17 of 24
(3)
where:
RF
OUT
is the RF frequency output.
INT
is the integer division factor.
FRAC
is the fractionality.
MOD
is the modulus.
F
PFD
=
REF
IN
× [(1 +
D)
/(
R ×
(
1+T
))]
(4)
where:
REF
IN
is the reference frequency input.
D
is the RF REF
IN
doubler bit.
T
is the reference divide-by-2 Bit(0 or 1).
R
is the RF reference division factor. For example, in a GSM
1800 system, where 1.8 GHz RF frequency output (RF
OUT
) is
required, a 13 MHz reference frequency input (REF
IN
) is
available, and a 200 kHz channel resolution (f
RES
) is required, on
the RF output.
MOD
=
REF
IN
/
f
RES
MOD
= 13 MHz/200 kHz = 65
From Equation 4
F
PFD
= [13 MHz × (1 + 0)/1] = 13 MHz
1.8 GHz = 13 MHz × (
INT
+
FRAC
/65)
where
INT
= 138;
FRAC
= 30.
(5)
(6)
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (f
RES
) required at
the RF output. For example, a GSM system with 13 MHz REF
IN
sets
the modulus to 65. This means that the RF output resolution (f
RES
)
is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,
the fractional spur interval depends on the modulus values chosen.
See Table 7 for more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot be operated above 32 MHz due to a
limitation in the speed of the Σ-Δ circuit of the N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4156 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configurations
for the application, when combined with the reference doubler
and the 5-bit R counter.
The following is an example of an application that requires
1.75 GHz RF and 200 kHz channel step resolution. The system
has a 13 MHz reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is a
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly to the PFD and
the modulus can be programmed to 520 when in PDC mode
(13 MHz/520 = 25 kHz).
The modulus needs to be reprogrammed to 65 for GSM 1800
operation (13 MHz/65 = 200 kHz).
It is important that the PFD frequency remains constant (13 MHz).
This allows the user to design one loop filter that can be used in
both setups without running into stability issues. It is the ratio
of the RF frequency to the PFD frequency that affects the loop
design. By keeping this relationship constant, the same loop
filter can be used in both applications.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
As mentioned in the Noise and Spur Mode section, the
ADF4156 can be optimized for noise performance. However, in
fast-locking applications, the loop bandwidth needs to be wide,
and therefore, the filter does not provide much attenuation of
the spurs. The cycle slip reduction function on the ADF4156
can be used to get around this issue. Using cycle slip reduction,
the loop bandwidth can be kept narrow to attenuate spurs and
still obtain fast lock times.
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| ADF4156BRUZ | 6 GHz Fractional-N Frequency Synthesizer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4156BCPZ-U1 | 制造商:Analog Devices 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Trays |
| ADF4156BRUZ | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4156BRUZ-RL | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156BRUZ-RL7 | 功能描述:IC PLL FRAC-N FREQ SYNTH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4156SP1BRUZ | 制造商:Analog Devices 功能描述: |
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