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參數(shù)資料
| 型號： | ADF4154 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Fractional-N Frequency Synthesizer |
| 中文描述： | 分?jǐn)?shù)N頻率合成器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ADF4154 |
ADF4154
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 9).
Figure 21 shows the MUXOUT section in block diagram form.
Rev. 0 | Page 10 of 20
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
ANALOG LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DV
DD
LOGIC LOW
FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
0
LOGIC HIGH
Figure 21. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4154 digital section includes a 4-bit RF R counter, a
9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the latches are programmed.
PROGRAM MODES
Table 5 through Table 10 show how to set up the program
modes in the ADF4154.
The ADF4154 programmable modulus is double-buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
then be written to so that the modulus value is loaded correctly.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
N-divider register
0
1
R-divider register
1
0
Control register
1
1
Noise and spur register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4154BCP | Fractional-N Frequency Synthesizer |
| ADF4154BCP-REEL | Fractional-N Frequency Synthesizer |
| ADF4154BCP-REEL7 | Fractional-N Frequency Synthesizer |
| ADF4154BRU | Fractional-N Frequency Synthesizer |
| ADF4154BRU-REEL | Fractional-N Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4154BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Bulk |
| ADF4154BCP-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Tape and Reel |
| ADF4154BCP-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
| ADF4154BCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4154BCPZ-RL | 功能描述:IC FRACTION-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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