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參數(shù)資料
| 型號： | ADF4153BCP-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Fractional-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 4000 MHz, QCC20 |
| 封裝： | 4 X 4 MM, MO-220VGGD-1, LFCSP-20 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 354K |
| 代理商： | ADF4153BCP-REEL7 |
ADF4153
Example: In a GSM 1800 system, where 1.8 GHz RF frequency
output (RF
OUT
) is required, a 13 MHz reference frequency input
(REF
IN
) is available and a 200 kHz channel resolution (f
RES
) is
required on the RF output.
Rev. A | Page 19 of 24
65
200
13
=
=
=
kHz
MHz
MOD
f
REF
MOD
RES
IN
From Equation 4:
(
(
)
[
13
]
MHz
MHz
F
PFD
13
1
0
1
=
+
×
=
(5)
)
30
;
138
65
13
8
INT
=
≥
=
≥
+
×
=
FRAC
FRAC
INT
MHz
G
(6)
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (f
RES
) required at
the RF output. For example, a GSM system with 13 MHz REF
IN
would set the modulus to 65. This means that the RF output
resolution (f
RES
) is the 200 kHz (13 MHz/65) necessary for GSM.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually results in an improvement in noise performance of 3 dB.
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the Σ-Δ circuit of
the N divider.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4153 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different
configurations for the application, when combined with the
reference doubler and the 4-bit R counter.
For example, here is an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This would
result in the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD. The modulus is now programmed to divide by
130. This also results in 200 kHz resolution and offers superior
phase noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC and
GSM 1800 standards, the programmable modulus is a huge
benefit. PDC requires 25 kHz channel step resolution, whereas
GSM 1800 requires 200 kHz channel step resolution. A 13 MHz
reference signal could be fed directly to the PFD. The modulus
would be programmed to 520 when in PDC mode (13 MHz/
520 = 25 kHz). The modulus would be reprogrammed to 65 for
GSM 1800 operation (13 MHz/65 = 200 kHz). It is important
that the PFD frequency remains constant (13 MHz). This allows
the user to design one loop filter that can be used in both setups
without running into stability issues. It is the ratio of the RF
frequency to the PFD frequency that affects the loop design.
Keeping this relationship constant, instead of changing the
modulus factor, results in a stable filter.
SPURIOUS OPTIMIZATION AND FASTLOCK
As mentioned earlier, the part can be optimized for spurious
performance. However, in fast locking applications, the loop
bandwidth needs to be wide, and therefore the filter does not
provide much attenuation of the spurs. The programmable
charge pump can be used to get around this issue. The filter is
designed for a narrow-loop bandwidth so that steady-state
spurious specifications are met. This is designed using the
lowest charge pump current setting. To implement fastlock
during a frequency jump, the charge pump current is set to the
maximum setting for the duration of the jump. This has the
effect of widening the loop bandwidth, which improves lock
time. When the PLL has locked to the new frequency, the charge
pump is again programmed to the lowest charge pump current
setting. This narrows the loop bandwidth to its original cutoff
frequency to allow better attenuation of the spurs than the
wide-loop bandwidth.
PHASE RESYNC AND SPUR CONSISTENCY
Setting the RESYNC bits [S4 ,S3, S2, and S1] enables the phase
RESYNC feature. With a fractional denominator of MOD, a
fractional-N PLL can settle with any one of (2 × π)/MOD valid
phase offsets with respect to the reference input. This is
different from integer-N where the RF output always settles to
the same static phase offset with respect to the input reference,
which is zero ideally. This is not an issue in applications that
require only a consistent frequency lock. When RESYNC is
enabled, it also ensures that spur levels remain consistent when
the PLL returns to a certain frequency. This is due to the fact
that the RESYNC function resets the Σ-Δ modulator. RESYNC
is enabled by setting the S4 to S1 bits in R2 to a nonzero value.
When the S4 to S1 bits are 0, 0, 0, and 0, RESYNC is disabled.
For applications where a consistent phase relationship between
the output and reference is required (i.e., digital beam forming),
the ADF4153 can be used with the phase resync feature enabled.
This ensures that if the user programs the PLL to jump from
Frequency (and Phase) A to Frequency (and Phase) B and back
again to Frequency A, the PLL returns to the original phase
(Phase A).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4153BRU | Fractional-N Frequency Synthesizer |
| ADF4153BRU-REEL | Fractional-N Frequency Synthesizer |
| ADF4153BRU-REEL7 | Fractional-N Frequency Synthesizer |
| ADF4154 | Fractional-N Frequency Synthesizer |
| ADF4154BCP | Fractional-N Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADF4153BCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 20-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4153BCPZ-RL | 功能描述:IC FRACTION-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4153BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4153BRU | 功能描述:IC SYNTH PLL RF F-N FREQ 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4153BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 16-Pin TSSOP T/R |
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