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參數(shù)資料
| 型號： | ADF4116 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器（PLL頻率合成器） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 77K |
| 代理商： | ADF4116 |
–5–
PRELMNARY
DATA
T able 3. R Counter Divide Ratios
TECHNCAL
Prelimnary Technical Data
ADF4116/ADF4117/ADF4118
Prelim D2 7/98
C IR C UIT D E SC R IP T ION
Input Shift Register
T he functional block diagram for the ADF4116 family is
shown on page 1. T he main blocks include a 21-bit input
shift register, a 14-bit R (Reference) counter and an 18-bit
N (A and B) counter. Data is clocked into the 21-bit shift
register on each rising edge of CLK . T he data is clocked
in MSB first. Data is transferred from the shift register to
one of four latches on the rising edge of LE. T he destina-
tion latch is determined by the state of the two control bits
(C2, C1) in the shift register. T hese are the two lsb's
DB1, DB0 as shown in the timing diagram of Figure 1.
T he truth table for these bits is shown below in T able 1.
T able 1. C2, C1 T ruth T able
C ontrol Bits
C 2
C 1
D ata L atch
0
0
1
1
0
1
0
1
R Counter Latch
N Counter Latch
Function L atch
Initialization L atch
Programmable R eference (R ) C ounter
If control bits C2, C1 are 0,0 then the data is transferred
from the input shift register to the R counter. T able 2
below shows the input shift register data format for pro-
gramming the R counter and T able 3 shows the divide
ratios possible.
Programmable D ivider (N C ounter
)
T he N counter consists of a 5-bit A counter (swallow
counter) and a 13-bit B counter (B counter). If C2, C1
are 0,1 the N counter is selected. T able 4 shows the
input register data format for programming the N counter.
T able 5 is the ADF4116 A counter truth table and T able
6 is the A counter truth table for the ADF4117 and
ADF4118. T able 7 shows the B counter truth table.
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LDP
T4
T3
T2
T1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
C2(0) C1(0)
NOT ES
1. T 1 to T 4 are test modes and should be zero for normal operation.
2. LDP is Lock Detect Precision. If this is set to a 1, then the internal lock detect circuitry takes 5 cycles instead of the normal 3 cycles for entering the
locked state.
3. Data is shifted in MSB (DB20) first.
Divide Ratio
1
2
*
*
16382
16383
R14
0
0
*
*
1
1
R13
0
0
*
*
1
1
R12
0
0
*
*
1
1
R11
0
0
*
*
1
1
R10
0
0
*
*
1
1
R9
0
0
*
*
1
1
R8
0
0
*
*
1
1
R7
0
0
*
*
1
1
R6
0
0
*
*
1
1
R5
0
0
*
*
1
1
R4
0
0
*
*
1
1
R3
0
0
*
*
1
1
R2
0
1
*
*
1
1
R1
1
0
*
*
0
1
NOT ES
1 Divide ratio: 1 to 16383
T able 4. Programming the N Counter
DB20
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CP Gaiin
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1
C2(0) C1(1)
T able 5. Swallow Counter (A Counter) for ADF4116
Divide
Ratio
0
1
*
7
A5
X
X
*
X
A4
X
X
*
X
A3
0
0
*
1
A2
0
0
*
1
A1
0
1
*
1
NOT ES
1.Divide ratio 0 to 7
2.B is greater than or equal to A
3.X equals Don't Care Condition
T able 6. Swallow Counter for ADF4117, ADF4118
Divide
Ratio
0
1
*
31
A5
0
0
*
1
A4
0
0
*
1
A3
0
0
*
1
A2
0
0
*
1
A1
0
1
*
1
NOT ES
1.Divide ratio 0 to 31
2.B is greater than or equal to A
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