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參數(shù)資料
| 型號(hào)： | ADF4113HVBRUZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | High Voltage Charge Pump, PLL Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3700 MHz, PDSO16 |
| 封裝： | LEAD FREE, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 385K |
| 代理商： | ADF4113HVBRUZ-RL |
ADF4113HV
Function Latch Map
Rev. 0 | Page 13 of 20
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P2
P1
0
0
0
0
CP3
CP2
CP1
0
0
0
0
0
0
F4
F3
M3
M2
M1
F2
F1
C2(1) C1(0)
CONTROL
BITS
C
S
P
P
PRE-
SCALER
VALUE
RESERVED
CURRENT
SETTING
RESERVED
MUXOUT
CONTROL
P
D
C
R
P2
0
0
1
1
P1
0
1
0
1
PRESCALER VALUE
8/9
16/17
32/33
64/65
I
CP
(μA)
4.7k
80
640
CPI3
0
1
CPI2
0
1
CPI1
0
1
F4
CHARGE PUMP
OUTPUT
0
1
NORMAL
THREE-STATE
F3
PHASE DETECTOR
POLARITY
0
1
POSITIVE
NEGATIVE
M3
0
0
M2
0
0
M1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
SERIAL DATA OUTPUT
DGND
PD1
0
1
OPERATION
NORMAL
POWER DOWN
F1
COUNTER
OPERATION
0
NORMAL
1
R, A, B COUNTERS
HELD IN RESET
0
Figure 22. Function Latch Map
FUNCTION LATCH
The on-chip function latch is programmed with C2 and C1 set
to 1,0, respectively. Figure 22 shows the input data format for
programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit must be disabled,
and the N counter resumes counting in close alignment with
the R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB3 (F2) in the function latch provides a software power-down
for the ADF4113HV. The device powers down immediately
after latching a 1 into Bit F2.
When the CE pin is low, the device immediately powers down
regardless of the state of the power-down bit (F2).
When a power-down is activated (either through software or
a CE pin activated power-down), the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RF
IN
A and RF
IN
B inputs are debiased.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4113HV. Figure 22 shows the truth table.
Charge Pump Currents
CPI3, CPI2, and CPI1 program the current setting for the
charge pump. The truth table is given in Figure 22.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid,
but a value of 8/9 is not.
PD Polarity
This bit sets the phase detector polarity bit. See Figure 22.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADF4113HVBRUZ-RL7 | 功能描述:IC CHARGE PUMP HV SYNTH 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113HVSD1Z | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4116 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4116BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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